| ee5b26fd | 01-May-2024 |
Andre Przywara <andre.przywara@arm.com> |
feat(allwinner): adjust H616 L2 cache size in DTB
The Allwinner H616 and its siblings come in different die revisions, some have 256 KB of L2 cache, some have 1 MB. This prevents a single static cac
feat(allwinner): adjust H616 L2 cache size in DTB
The Allwinner H616 and its siblings come in different die revisions, some have 256 KB of L2 cache, some have 1 MB. This prevents a single static cache description in the devicetree.
Use the cache size ID register (CCSIDR_EL1) to query the topology of the L2 cache, and adjust the cache-sets and cache-size properties in the L2 cache DT node accordingly.
The ARM ARM does not promise (anymore) that the cache size can be derived *architecturally* from this register, but the reading is definitely correct for the Arm Cortex-A53 core used.
Change-Id: Id7dc324d783b8319fe5df6164be2f941d4cac82d Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| 646d06b2 | 21-Mar-2024 |
Andre Przywara <andre.przywara@arm.com> |
feat(allwinner): h616: add support for AXP717 PMIC
On at least one new device we see an Allwinner H700 SoC paired with the X-Powers AXP717 PMIC. In contrast to the small AXP313, this is a quite comp
feat(allwinner): h616: add support for AXP717 PMIC
On at least one new device we see an Allwinner H700 SoC paired with the X-Powers AXP717 PMIC. In contrast to the small AXP313, this is a quite complete PMIC, with many voltage rails, battery and USB-C charging support. It supports both RSB and I2C control options.
Add the compatible string to the list of checked devices. The AXP717 apparently does not feature a version ID register, but we read 0xff from that address 0x3, so use this as an indication of its presence, since this value differs from what we read from the other PMICs. The register offset and bit position for the power off functionality is again different, but easy to put into our switch/case.
Setting up regulators in TF-A is now somewhat obsolete, since U-Boot does a much better job in this now, and can figure out which regulators are actually needed. So we don't add the regulator setup code, and just use the PMIC for the power-off functionality.
Change-Id: Ie6b4c91517014adcc79d9a3459c75545fa3a63e6 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| 03851367 | 21-Mar-2024 |
Andre Przywara <andre.przywara@arm.com> |
feat(allwinner): h616: add support for AXP313 PMIC
Many newer boards with the H616 and its sibling H618 are now paired with the X-Powers AXP313 PMIC. This is a simpler PMIC, with only a few voltage
feat(allwinner): h616: add support for AXP313 PMIC
Many newer boards with the H616 and its sibling H618 are now paired with the X-Powers AXP313 PMIC. This is a simpler PMIC, with only a few voltage rails and no extra functionality except the power key support. In contrast to the AXP305 it can only be controlled via I2C.
Add a check to look for the AXP313 compatible string in the devicetree, and set the PMIC type and I2C address accordingly, if one is found. With only very few voltage rails available, all of them are mostly in use and are thus enabled at reset already, so we can skip the regulator setup entirely.
Change-Id: I01962854109e43793b4f56553c1ca9e1f752e30d Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| 04445898 | 21-Mar-2024 |
Andre Przywara <andre.przywara@arm.com> |
feat(allwinner): h616: add I2C PMIC support
The X-Powers AXP305 PMIC can be controlled via both I2C or RSB (an Allwinner specific bus similar to I2C), but we chose to use only RSB, because that's ea
feat(allwinner): h616: add I2C PMIC support
The X-Powers AXP305 PMIC can be controlled via both I2C or RSB (an Allwinner specific bus similar to I2C), but we chose to use only RSB, because that's easier to program and also used by Linux. The AXP313a PMIC however supports only I2C, so we need to support both buses, and need to decide which to use at runtime.
Prepare the PMIC code to add (back) I2C support. We initially used I2C on the H6/AXP805 combination, but replaced that later with RSB. So this patch is bringing some of that older code back.
The decision whether to use I2C or RSB is made by the devicetree, since on some boards even RSB capable PMICs are controlled via I2C, since they share the bus with only I2C capable devices, for instance RTCs.
At the moment this will still use RSB to drive the AXP305, but the (dynamic) I2C code will be used shortly to support the AXP313.
This increases the code size by one 4K page, but with 80K out of the reserved 256K we are still very far away from our limit.
Change-Id: I65c1e7df93dbd2dcd171b3fc486533a2948cc75b Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| fbde260b | 03-Apr-2023 |
Andre Przywara <andre.przywara@arm.com> |
feat(allwinner): add function to detect H616 die variant
Allwinner provides a number of SoCs that use the same die as the H616. Some of those chips apparently use a slight variation of that die, tha
feat(allwinner): add function to detect H616 die variant
Allwinner provides a number of SoCs that use the same die as the H616. Some of those chips apparently use a slight variation of that die, that differs in the way the CPU cores' power and reset controls are handled. This die variation can be detected by reading the SRAM version register.
Provide a predicate function that returns false if that die variant is used. Since the CPU power control code is shared for all supported SoCs, we provide an instance of this function for each SoC, as a static inline, and return true on all other SoCs. This allows to always use this function, and still let the compiler optimise away the unneeded branch for those older SoCs.
This function is unused for now, but is needed in the next patch.
Change-Id: I49e014b895b7e2f55b4e7dc2b3d8aa31cee711b5 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| b15e2cda | 09-Dec-2022 |
Mikhail Kalashnikov <iuncuim@gmail.com> |
feat(allwinner): add extra CPU control registers
The die used in several variants of the Allwinner H616 SoC (H313, T507) seems to produced in at least two revisions. The newer one differs from the o
feat(allwinner): add extra CPU control registers
The die used in several variants of the Allwinner H616 SoC (H313, T507) seems to produced in at least two revisions. The newer one differs from the original by using a different CPU control register IP block.
Add those newly used register offsets to the respective header file. The MMIO block itself is actually present in both variants, though the registers are different. The new registers tend to use one register per core, in contrast to one register per cluster in the older revisions.
Change-Id: Ifbda1bdc67a6a16fbb901dbc83996e4a148b7602 Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| 0be10ee3 | 14-Dec-2020 |
Andre Przywara <andre.przywara@arm.com> |
allwinner: H616: Add reserved-memory node to DT
When the BL31 for the Allwinner H616 runs in DRAM, we need to make sure we tell the non-secure world about the memory region it uses.
Add a reserved-
allwinner: H616: Add reserved-memory node to DT
When the BL31 for the Allwinner H616 runs in DRAM, we need to make sure we tell the non-secure world about the memory region it uses.
Add a reserved-memory node to the DT, which covers the area that BL31 could occupy. The "no-map" property will prevent OSes from mapping the area, so there would be no speculative accesses.
Change-Id: I808f3e1a8089da53bbe4fc6435a808e9159831e1 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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