Merge changes from topic "allwinner_t507" into integration

* changes:
feat(allwinner): add support for Allwinner T507 SoC
feat(allwinner): add function to detect H616 die variant
feat(allwinne

Merge changes from topic "allwinner_t507" into integration

* changes:
feat(allwinner): add support for Allwinner T507 SoC
feat(allwinner): add function to detect H616 die variant
feat(allwinner): add extra CPU control registers
refactor(allwinner): consolidate sunxi_cfg.h files

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feat(allwinner): add extra CPU control registers

The die used in several variants of the Allwinner H616 SoC (H313, T507)
seems to produced in at least two revisions. The newer one differs from
the o

feat(allwinner): add extra CPU control registers

The die used in several variants of the Allwinner H616 SoC (H313, T507)
seems to produced in at least two revisions. The newer one differs from
the original by using a different CPU control register IP block.

Add those newly used register offsets to the respective header file. The
MMIO block itself is actually present in both variants, though the
registers are different. The new registers tend to use one register per
core, in contrast to one register per cluster in the older revisions.

Change-Id: Ifbda1bdc67a6a16fbb901dbc83996e4a148b7602
Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes from topic "allwinner-r329" into integration

* changes:
feat(plat/allwinner): add R329 support
refactor(plat/allwinner): allow custom BL31 offset
refactor(plat/allwinner): allow

Merge changes from topic "allwinner-r329" into integration

* changes:
feat(plat/allwinner): add R329 support
refactor(plat/allwinner): allow custom BL31 offset
refactor(plat/allwinner): allow new AA64nAA32 position
fix(plat/allwinner): delay after enabling CPU power

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refactor(plat/allwinner): allow custom BL31 offset

Not all Allwinner SoCs have the same arrangement to SRAM A2.

Allow to specify a offset at which BL31 will stay in SRAM A2.

Change-Id: I574140ffd7

refactor(plat/allwinner): allow custom BL31 offset

Not all Allwinner SoCs have the same arrangement to SRAM A2.

Allow to specify a offset at which BL31 will stay in SRAM A2.

Change-Id: I574140ffd704a796fae0a5c2d0976e85c7fcbdf9
Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>

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Merge changes I3703868b,Ie77476db into integration

* changes:
allwinner: Add SPC security setup for H6
allwinner: Add R_PRCM security setup for H6

Merge changes I0c5f32e8,Id49c124c,Idcfe933d into integration

* changes:
allwinner: Use RSB for the PMIC connection on H6
allwinner: Return the PMIC to I2C mode after use
allwinner: Always use

Merge changes I0c5f32e8,Id49c124c,Idcfe933d into integration

* changes:
allwinner: Use RSB for the PMIC connection on H6
allwinner: Return the PMIC to I2C mode after use
allwinner: Always use a 3MHz RSB bus clock

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allwinner: Use RSB for the PMIC connection on H6

RSB is faster and more efficient, and it has a simpler driver. As long
as the PMIC is returned to I2C mode after use, the rich OS can later use
eithe

allwinner: Use RSB for the PMIC connection on H6

RSB is faster and more efficient, and it has a simpler driver. As long
as the PMIC is returned to I2C mode after use, the rich OS can later use
either bus.

Change-Id: I0c5f32e88a090c8c5cccb81bd24596b301ab9da7
Signed-off-by: Samuel Holland <samuel@sholland.org>

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allwinner: Add SPC security setup for H6

The H6 has a "secure port controller" similar to the A64/H5, but with
more ports and a different register layout. Split the platform-specific
parts out into

allwinner: Add SPC security setup for H6

The H6 has a "secure port controller" similar to the A64/H5, but with
more ports and a different register layout. Split the platform-specific
parts out into a header, and add the missing MMIO base address.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I3703868bc595459ecf9568b9d1605cb1be014bf5

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allwinner: Add R_PRCM security setup for H6

H6 has a reorganized R_PRCM compared to A64/H5, with the security switch
at a different offset. Until now, we did not notice, because the switch
has no ef

allwinner: Add R_PRCM security setup for H6

H6 has a reorganized R_PRCM compared to A64/H5, with the security switch
at a different offset. Until now, we did not notice, because the switch
has no effect unless the secure mode e-fuse is blown.

Since we are adding more platform-specific CCU registers, move them to
their own header, and out of the memory map (where they do not belong).

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ie77476db0515080954eaa2e32bf6c3de657cda86

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Merge "allwinner: H6: Fix GPIO and CCU memory map addresses" into integration

allwinner: H6: Fix GPIO and CCU memory map addresses

The base address for both the GPIO and the clock unit of the H6 memory map
have been typo-ed. Fix them to match the Linux DT and the manual.

The

allwinner: H6: Fix GPIO and CCU memory map addresses

The base address for both the GPIO and the clock unit of the H6 memory map
have been typo-ed. Fix them to match the Linux DT and the manual.

The H6 code use neither of them, so this doesn't change or fix anything
in the real world, but should be corrected anyway.

The issue was found and reported by Github user "armlabs".

Change-Id: Ic6fdfb732ce1cfc54cbb927718035624a06a9e08
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "allwinner: Adjust SRAM A2 base to include the ARISC vectors" into integration

allwinner: Adjust SRAM A2 base to include the ARISC vectors

The ARISC vector area consists of 0x4000 bytes before the beginning of
usable SRAM. Still, it is technically a part of SRAM A2, so include

allwinner: Adjust SRAM A2 base to include the ARISC vectors

The ARISC vector area consists of 0x4000 bytes before the beginning of
usable SRAM. Still, it is technically a part of SRAM A2, so include it
in the memory definition. This avoids the confusing practice of
subtracting from the beginning of the SRAM region when referencing the
ARISC vectors.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Iae89e01aeab93560159562692e03e88306e2a1bf

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Merge pull request #1673 from antonio-nino-diaz-arm/an/headers

Standardise header guards across codebase

Standardise header guards across codebase

All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.

The style that this proje

Standardise header guards across codebase

All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.

The style that this project is now to use the full name of the file in
capital letters followed by 'H'. For example, for a file called
"uart_example.h", the header guard is UART_EXAMPLE_H.

The exceptions are files that are imported from other projects:

- CryptoCell driver
- dt-bindings folders
- zlib headers

Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1646 from Andre-ARM/allwinner/pmic-v2

Allwinner/pmic v2

allwinner: H6: Fix SRAM size

The SRAM in the Allwinner H6 SoC starts at 0x2000, with the last part
ending at 0x117fff (although with gaps in between).
So SUNXI_SRAM_SIZE should be 0xf8000, not 0x980

allwinner: H6: Fix SRAM size

The SRAM in the Allwinner H6 SoC starts at 0x2000, with the last part
ending at 0x117fff (although with gaps in between).
So SUNXI_SRAM_SIZE should be 0xf8000, not 0x98000.

Fix this to map the arisc exception vector area, which we will need
shortly.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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allwinner: Adjust memory mapping to fit into 256MB

At the moment we map as much of the DRAM into EL3 as possible, however
we actually don't use it. The only exception is the secure DRAM for
BL32 (if

allwinner: Adjust memory mapping to fit into 256MB

At the moment we map as much of the DRAM into EL3 as possible, however
we actually don't use it. The only exception is the secure DRAM for
BL32 (if that is configured).

To decrease the memory footprint of ATF, we save on some page tables by
reducing the memory mapping to the actually required regions: SRAM, device
MMIO, secure DRAM and U-Boot (to be used later).
This introduces a non-identity mapping for the DRAM regions.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge pull request #1465 from Andre-ARM/allwinner/h6-support

allwinner: Add H6 SoC support

allwinner: Add Allwinner H6 SoC support

The H6 is Allwinner's most recent SoC. It shares most peripherals with the
other ARMv8 Allwinner SoCs (A64/H5), but has a completely different memory
map.

In

allwinner: Add Allwinner H6 SoC support

The H6 is Allwinner's most recent SoC. It shares most peripherals with the
other ARMv8 Allwinner SoCs (A64/H5), but has a completely different memory
map.

Introduce a separate platform target, which includes a different header
file to cater for the address differences. Also add the new build target
to the documentation.

The new ATF platform name is "sun50i_h6".

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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