| c4143b74 | 21-Jun-2018 |
Andre Przywara <andre.przywara@arm.com> |
allwinner: Detect and output current SoC
So far we already support booting on two different SoCs, and we will
shortly add a third, so add some code to determine the current SoC type.
This can be lat
allwinner: Detect and output current SoC
So far we already support booting on two different SoCs, and we will
shortly add a third, so add some code to determine the current SoC type.
This can be later used to runtime detect certain properties.
Also print the SoC name to the console, to give valuable debug information.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| ae903c56 | 21-Jun-2018 |
Andre Przywara <andre.przywara@arm.com> |
allwinner: Don't map boot ROM
There is nothing we need from the BootROM area, so we also don't need
to map it in EL3.
Remove the mapping and reduce the number of MMAP regions by one.
Reported-by:
allwinner: Don't map boot ROM
There is nothing we need from the BootROM area, so we also don't need
to map it in EL3.
Remove the mapping and reduce the number of MMAP regions by one.
Reported-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| c520be4b | 21-Jun-2018 |
Andre Przywara <andre.przywara@arm.com> |
allwinner: Relax PSCI entry point check
The DRAM controller supports up to 4GB of DRAM, and there are actually
boards out there where we can use at least 3GB of this.
Relax the PSCI entry point che
allwinner: Relax PSCI entry point check
The DRAM controller supports up to 4GB of DRAM, and there are actually
boards out there where we can use at least 3GB of this.
Relax the PSCI entry point check, to be not restricted to 2GB of DRAM.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| 88aa5c43 | 21-Jun-2018 |
Andre Przywara <andre.przywara@arm.com> |
allwinner: security: Fix SPC guard
The "#ifdef SUNXI_SPC_BASE" guard was meant to allow the build on SoCs
without a Secure Peripherals Controller, so that we skip that part of
the security setup. Bu
allwinner: security: Fix SPC guard
The "#ifdef SUNXI_SPC_BASE" guard was meant to allow the build on SoCs
without a Secure Peripherals Controller, so that we skip that part of
the security setup. But in the current position this will trigger a
warning about an unused variable.
Simply move the guard one line up to cover the variable as well.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| 27f9616f | 22-Jun-2018 |
Andre Przywara <andre.przywara@arm.com> |
allwinner: cpu-ops: avoid PSCI on/off output
The "INFO" output in sunxi_cpu_ops.c is quite verbose, so make this more
obvious by changing the log level to "VERBOSE" and so avoiding it to
be printed
allwinner: cpu-ops: avoid PSCI on/off output
The "INFO" output in sunxi_cpu_ops.c is quite verbose, so make this more
obvious by changing the log level to "VERBOSE" and so avoiding it to
be printed in a normal (even debug) build.
Reported-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| 6daab88f | 21-Jun-2018 |
Andre Przywara <andre.przywara@arm.com> |
allwinner: common: add missing header
Some code in sunxi_common.c requires symbols defined in sunxi_private.h,
so add the header to that file.
It was included via another header before, but let's ma
allwinner: common: add missing header
Some code in sunxi_common.c requires symbols defined in sunxi_private.h,
so add the header to that file.
It was included via another header before, but let's make this explicit.
Reported-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| acb8b3ca | 01-Jun-2018 |
Andre Przywara <andre.przywara@arm.com> |
allwinner: Add security setup
Some peripherals are TrustZone aware, so they need to be configured to
be accessible from non-secure world, as we don't need any of them being
exclusive to the secure w
allwinner: Add security setup
Some peripherals are TrustZone aware, so they need to be configured to
be accessible from non-secure world, as we don't need any of them being
exclusive to the secure world.
This affects some clocks, DMA channels and the Secure Peripheral
Controller (SPC). The latter controls access to most devices, but is not
active unless booting with the secure boot fuse burnt.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| 560581ec | 12-Aug-2017 |
Samuel Holland <samuel@sholland.org> |
allwinner: Add platform PSCI functions required for SMP
The reset vector entry point is preserved across CPU resets, so it only
needs to be set once at boot.
Hotplugged CPUs are not actually powere
allwinner: Add platform PSCI functions required for SMP
The reset vector entry point is preserved across CPU resets, so it only
needs to be set once at boot.
Hotplugged CPUs are not actually powered down, but are put in a wfi with
the GIC disconnected.
With this commit, Linux is able to enable, hotplug and use all four CPUs.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| 333d66cf | 12-Aug-2017 |
Samuel Holland <samuel@sholland.org> |
allwinner: Add functions to control CPU power/reset
sun50i_cpu_on will be used by the PSCI implementation to initialize
secondary cores for SMP. Unfortunately, sun50i_cpu_off is not usable by
PSCI d
allwinner: Add functions to control CPU power/reset
sun50i_cpu_on will be used by the PSCI implementation to initialize
secondary cores for SMP. Unfortunately, sun50i_cpu_off is not usable by
PSCI directly, because it is not possible for a CPU to use this function
to power itself down. Power cannot be shut off until the outputs are
clamped, and MMIO does not work once the outputs are clamped.
But at least CPU0 can shutdown the other cores early in the BL31 boot
process and before shutting down the system.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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