| #
b3210f4d |
| 17-Sep-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "TrcDbgExt" into integration
* changes:
feat(plat/fvp): enable trace extension features by default
feat(trf): enable trace filter control register access from lower NS E
Merge changes from topic "TrcDbgExt" into integration
* changes:
feat(plat/fvp): enable trace extension features by default
feat(trf): enable trace filter control register access from lower NS EL
feat(trf): initialize trap settings of trace filter control registers access
feat(sys_reg_trace): enable trace system registers access from lower NS ELs
feat(sys_reg_trace): initialize trap settings of trace system registers access
feat(trbe): enable access to trace buffer control registers from lower NS EL
feat(trbe): initialize trap settings of trace buffer control registers access
show more ...
|
| #
8fcd3d96 |
| 08-Jul-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(trf): enable trace filter control register access from lower NS EL
Introduced a build flag 'ENABLE_TRF_FOR_NS' to enable trace filter
control registers access in NS-EL2, or NS-EL1 (when NS-EL2
feat(trf): enable trace filter control register access from lower NS EL
Introduced a build flag 'ENABLE_TRF_FOR_NS' to enable trace filter
control registers access in NS-EL2, or NS-EL1 (when NS-EL2 is
implemented but unused).
Change-Id: If3f53b8173a5573424b9a405a4bd8c206ffdeb8c
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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|
| #
d4582d30 |
| 29-Jun-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(sys_reg_trace): enable trace system registers access from lower NS ELs
Introduced a build flag 'ENABLE_SYS_REG_TRACE_FOR_NS' to enable trace
system registers access in NS-EL2, or NS-EL1 (when N
feat(sys_reg_trace): enable trace system registers access from lower NS ELs
Introduced a build flag 'ENABLE_SYS_REG_TRACE_FOR_NS' to enable trace
system registers access in NS-EL2, or NS-EL1 (when NS-EL2 is
implemented but unused).
Change-Id: Idc1acede4186e101758cbf7bed5af7b634d7d18d
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
show more ...
|
| #
813524ea |
| 02-Jul-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(trbe): enable access to trace buffer control registers from lower NS EL
Introduced a build flag 'ENABLE_TRBE_FOR_NS' to enable trace buffer
control registers access in NS-EL2, or NS-EL1 (when N
feat(trbe): enable access to trace buffer control registers from lower NS EL
Introduced a build flag 'ENABLE_TRBE_FOR_NS' to enable trace buffer
control registers access in NS-EL2, or NS-EL1 (when NS-EL2 is
implemented but unused).
Change-Id: I285a672ccd395eebd377714c992bb21062a729cc
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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|
| #
5e4e13e1 |
| 02-Aug-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "fw-update-2" into integration
* changes:
feat(sw_crc32): add software CRC32 support
refactor(hw_crc32): renamed hw_crc32 to tf_crc32
feat(fwu): avoid booting with an
Merge changes from topic "fw-update-2" into integration
* changes:
feat(sw_crc32): add software CRC32 support
refactor(hw_crc32): renamed hw_crc32 to tf_crc32
feat(fwu): avoid booting with an alternate boot source
docs(fwu): add firmware update documentation
feat(fwu): avoid NV counter upgrade in trial run state
feat(plat/arm): add FWU support in Arm platforms
feat(fwu): initialize FWU driver in BL2
feat(fwu): add FWU driver
feat(fwu): introduce FWU platform-specific functions declarations
docs(fwu_metadata): add FWU metadata build options
feat(fwu_metadata): add FWU metadata header and build options
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|
| #
396b339d |
| 25-Jun-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(fwu): initialize FWU driver in BL2
Initialized FWU driver module in BL2 component under
build flag PSA_FWU_SUPPORT.
Change-Id: I08b191599835925c355981d695667828561b9a21
Signed-off-by: Manish V
feat(fwu): initialize FWU driver in BL2
Initialized FWU driver module in BL2 component under
build flag PSA_FWU_SUPPORT.
Change-Id: I08b191599835925c355981d695667828561b9a21
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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|
| #
5357f83d |
| 16-Mar-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(fwu_metadata): add FWU metadata header and build options
Added a firmware update metadata structure as per section 4.1
in the specification document[1].
Also, added the build options used in d
feat(fwu_metadata): add FWU metadata header and build options
Added a firmware update metadata structure as per section 4.1
in the specification document[1].
Also, added the build options used in defining the firmware
update metadata structure.
[1]: https://developer.arm.com/documentation/den0118/a/
Change-Id: I8f43264a46fde777ceae7fd2a5bb0326f1711928
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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|
| #
81a8b2da |
| 30-Jun-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "feat(sve): enable SVE for the secure world" into integration
|
| #
0c5e7d1c |
| 22-Mar-2021 |
Max Shvetsov <maksims.svecovs@arm.com> |
feat(sve): enable SVE for the secure world
Enables SVE support for the secure world via ENABLE_SVE_FOR_SWD.
ENABLE_SVE_FOR_SWD defaults to 0 and has to be explicitly set by the
platform. SVE is conf
feat(sve): enable SVE for the secure world
Enables SVE support for the secure world via ENABLE_SVE_FOR_SWD.
ENABLE_SVE_FOR_SWD defaults to 0 and has to be explicitly set by the
platform. SVE is configured during initial setup and then uses EL3
context save/restore routine to switch between SVE configurations for
different contexts.
Reset value of CPTR_EL3 changed to be most restrictive by default.
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: I889fbbc2e435435d66779b73a2d90d1188bf4116
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|
| #
e55d12b7 |
| 27-May-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "Arm_PCI_Config_Space_Interface" into integration
* changes:
TF-A: Document SMC_PCI_SUPPORT option
SMCCC/PCI: Handle std svc boilerplate
SMCCC/PCI: Add initial PCI con
Merge changes from topic "Arm_PCI_Config_Space_Interface" into integration
* changes:
TF-A: Document SMC_PCI_SUPPORT option
SMCCC/PCI: Handle std svc boilerplate
SMCCC/PCI: Add initial PCI conduit definitions
SMCCC: Hoist SMC_32 sanitization
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|
| #
c7a28aa7 |
| 18-Nov-2020 |
Jeremy Linton <jeremy.linton@arm.com> |
SMCCC/PCI: Add initial PCI conduit definitions
Add constants, structures and build definition for the
new standard SMCCC PCI conduit. These are documented
in DEN0115A.
https://developer.arm.com/doc
SMCCC/PCI: Add initial PCI conduit definitions
Add constants, structures and build definition for the
new standard SMCCC PCI conduit. These are documented
in DEN0115A.
https://developer.arm.com/documentation/den0115/latest
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Change-Id: If667800a26b9ae88626e8d895674c9c2e8c09658
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|
| #
ef4c1e19 |
| 02-Mar-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "Enable v8.6 AMU enhancements (FEAT_AMUv1p1)" into integration
|
| #
873d4241 |
| 02-Oct-2020 |
johpow01 <john.powell@arm.com> |
Enable v8.6 AMU enhancements (FEAT_AMUv1p1)
ARMv8.6 adds virtual offset registers to support virtualization of the
event counters in EL1 and EL0. This patch enables support for this
feature in EL3
Enable v8.6 AMU enhancements (FEAT_AMUv1p1)
ARMv8.6 adds virtual offset registers to support virtualization of the
event counters in EL1 and EL0. This patch enables support for this
feature in EL3 firmware.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7ee1f3d9f554930bf5ef6f3d492e932e6d95b217
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|
| #
6080aac9 |
| 05-Feb-2021 |
André Przywara <andre.przywara@arm.com> |
Merge "Add TRNG Firmware Interface service" into integration
|
| #
7dfb9911 |
| 22-Jun-2020 |
Jimmy Brisson <jimmy.brisson@arm.com> |
Add TRNG Firmware Interface service
This adds the TRNG Firmware Interface Service to the standard
service dispatcher. This includes a method for dispatching entropy
requests to platforms and include
Add TRNG Firmware Interface service
This adds the TRNG Firmware Interface Service to the standard
service dispatcher. This includes a method for dispatching entropy
requests to platforms and includes an entropy pool implementation to
avoid dropping any entropy requested from the platform.
Change-Id: I71cadb3cb377a507652eca9e0d68714c973026e9
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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|
| #
29a8814f |
| 15-Dec-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "Add support for FEAT_MTPMU for Armv8.6" into integration
|
| #
de155790 |
| 11-Dec-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "TF-A: Add build option for Arm Feature Modifiers" into integration
|
| #
0063dd17 |
| 23-Nov-2020 |
Javier Almansa Sobrino <javier.almansasobrino@arm.com> |
Add support for FEAT_MTPMU for Armv8.6
If FEAT_PMUv3 is implemented and PMEVTYPER<n>(_EL0).MT bit is implemented
as well, it is possible to control whether PMU counters take into account
events happ
Add support for FEAT_MTPMU for Armv8.6
If FEAT_PMUv3 is implemented and PMEVTYPER<n>(_EL0).MT bit is implemented
as well, it is possible to control whether PMU counters take into account
events happening on other threads.
If FEAT_MTPMU is implemented, EL3 (or EL2) can override the MT bit
leaving it to effective state of 0 regardless of any write to it.
This patch introduces the DISABLE_MTPMU flag, which allows to diable
multithread event count from EL3 (or EL2). The flag is disabled
by default so the behavior is consistent with those architectures
that do not implement FEAT_MTPMU.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: Iee3a8470ae8ba13316af1bd40c8d4aa86e0cb85e
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|
| #
f1821790 |
| 07-Dec-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
TF-A: Add build option for Arm Feature Modifiers
This patch adds a new ARM_ARCH_FEATURE build option
to add support for compiler's feature modifiers.
It has the form '[no]feature+...' and defaults t
TF-A: Add build option for Arm Feature Modifiers
This patch adds a new ARM_ARCH_FEATURE build option
to add support for compiler's feature modifiers.
It has the form '[no]feature+...' and defaults to
'none'. This option translates into compiler option
'-march=armvX[.Y]-a+[no]feature+...'.
Change-Id: I37742f270a898f5d6968e146cbcc04cbf53ef2ad
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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|
| #
c4d919ee |
| 21-Oct-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "tc0_sel2_spmc" into integration
* changes:
lib: el3_runtime: Fix SPE system registers in el2_sysregs_context
lib: el3_runtime: Conditionally save/restore EL2 NEVE regis
Merge changes from topic "tc0_sel2_spmc" into integration
* changes:
lib: el3_runtime: Fix SPE system registers in el2_sysregs_context
lib: el3_runtime: Conditionally save/restore EL2 NEVE registers
lib: el3_runtime: Fix aarch32 system registers in el2_sysregs_context
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|
| #
062f8aaf |
| 28-May-2020 |
Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> |
lib: el3_runtime: Conditionally save/restore EL2 NEVE registers
Include EL2 registers related to Nested Virtualization in EL2 context
save/restore routines if architecture supports it and platform w
lib: el3_runtime: Conditionally save/restore EL2 NEVE registers
Include EL2 registers related to Nested Virtualization in EL2 context
save/restore routines if architecture supports it and platform wants to
use these features in Secure world.
Change-Id: If006ab83bbc2576488686f5ffdff88b91adced5c
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
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|
| #
e1b8cd1a |
| 12-Oct-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "TF-A: Add HASH_ALG default value to defaults.mk" into integration
|
| #
ae3cf1ff |
| 06-Oct-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
TF-A: Add HASH_ALG default value to defaults.mk
This patch adds default value of 'sha256' for HASH_ALG
build flag to 'make_helpers\defaults.mk', according to
'docs\getting_started\build-options.rst'
TF-A: Add HASH_ALG default value to defaults.mk
This patch adds default value of 'sha256' for HASH_ALG
build flag to 'make_helpers\defaults.mk', according to
'docs\getting_started\build-options.rst'.
This fixes Measured Boot driver error when TF-A uses
default HASH_ALG value and TPM_HASH_ALG is set to
sha384 or sha512.
Change-Id: Id0aa34b54807de0adaf88e5f7d7032577c22f365
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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|
| #
8c00bcce |
| 21-Sep-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "defaults.mk: default KEY_SIZE to 2048 in case of RSA algorithm" into integration
|
| #
ee15a172 |
| 18-Jun-2020 |
Leonardo Sandoval <leonardo.sandoval@linaro.org> |
defaults.mk: default KEY_SIZE to 2048 in case of RSA algorithm
According to the documentation [1], KEY_SIZE defaults to 2048 when RSA
algorithm is chosen, so set this value on the make's defaults fi
defaults.mk: default KEY_SIZE to 2048 in case of RSA algorithm
According to the documentation [1], KEY_SIZE defaults to 2048 when RSA
algorithm is chosen, so set this value on the make's defaults file.
[1] https://trustedfirmware-a.readthedocs.io/en/latest/getting_started/build-options.html
Change-Id: I030f98363198a752bc0dd03528f748de527d48d8
Signed-off-by: Leonardo Sandoval <leonardo.sandoval@linaro.org>
show more ...
|