| #
3995f30c |
| 27-Jun-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "refactor(build): merge march32/64 directives" into integration
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| #
d4089fb8 |
| 30-May-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
refactor(build): merge march32/64 directives
Both march32-directive and march64-directive eventually generate the
same march option that will passed to compiler.
Merge this two separate directives
refactor(build): merge march32/64 directives
Both march32-directive and march64-directive eventually generate the
same march option that will passed to compiler.
Merge this two separate directives to a common one as march-directive.
Change-Id: I220d2b782eb3b54e13ffd5b6a581d0e6da68756a
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| #
c1a4b6b4 |
| 21-Sep-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "build_macros.mk: include assert and define loop macros" into integration
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| #
327131c4 |
| 10-Sep-2020 |
Leonardo Sandoval <leonardo.sandoval@linaro.org> |
build_macros.mk: include assert and define loop macros
Loop macros make it easier for developers to include new variables to
assert or define and also help code code readability on makefiles.
Chang
build_macros.mk: include assert and define loop macros
Loop macros make it easier for developers to include new variables to
assert or define and also help code code readability on makefiles.
Change-Id: I0d21d6e67b3eca8976c4d856ac8ccc02c8bb5ffa
Signed-off-by: Leonardo Sandoval <leonardo.sandoval@linaro.org>
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| #
5ba32a76 |
| 21-Feb-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1828 from uarif1/master
Introduce Versatile Express FVP platform to arm-trusted-firmware.
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| #
8f73663b |
| 12-Dec-2018 |
Usama Arif <usama.arif@arm.com> |
plat/arm: Support for Cortex A5 in FVP Versatile Express platform
Cortex A5 doesnt support VFP, Large Page addressing and generic timer
which are addressed in this patch. The device tree for Cortex
plat/arm: Support for Cortex A5 in FVP Versatile Express platform
Cortex A5 doesnt support VFP, Large Page addressing and generic timer
which are addressed in this patch. The device tree for Cortex a5
is also included.
Change-Id: I0722345721b145dfcc80bebd36a1afbdc44bb678
Signed-off-by: Usama Arif <usama.arif@arm.com>
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| #
71f8a6a9 |
| 23-Nov-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1145 from etienne-lms/rfc-armv7-2
Support ARMv7 architectures
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| #
86e26835 |
| 08-Nov-2017 |
Etienne Carriere <etienne.carriere@linaro.org> |
ARMv7 may not support Generic Timer Extension
If ARMv7 based platform does not set ARM_CORTEX_Ax=yes, platform
shall define ARMV7_SUPPORTS_GENERIC_TIMER to enable generic timer
support.
Signed-off-
ARMv7 may not support Generic Timer Extension
If ARMv7 based platform does not set ARM_CORTEX_Ax=yes, platform
shall define ARMV7_SUPPORTS_GENERIC_TIMER to enable generic timer
support.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| #
64cc6e91 |
| 08-Nov-2017 |
Etienne Carriere <etienne.carriere@linaro.org> |
ARMv7 may not support Virtualization Extensions
ARMv7-A Virtualization extensions brings new instructions and resources
that were supported by later architectures. Reference ARM ARM Issue C.c
[DDI04
ARMv7 may not support Virtualization Extensions
ARMv7-A Virtualization extensions brings new instructions and resources
that were supported by later architectures. Reference ARM ARM Issue C.c
[DDI0406C_C].
ERET and extended MSR/MRS instructions, as specified in [DDI0406C_C] in
ID_PFR1 description of bits[15:12] (Virtualization Extensions):
A value of 0b0001 implies implementation of the HVC, ERET, MRS
(Banked register), and MSR (Banked register) instructions. The ID_ISARs
do not identify whether these instructions are implemented.
UDIV/SDIV were introduced with the Virtualization extensions, even if
not strictly related to the virtualization extensions.
If ARMv7 based platform does not set ARM_CORTEX_Ax=yes, platform
shall define ARMV7_SUPPORTS_VIRTUALIZATION to enable virtualization
extension related resources.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| #
51b992ec |
| 08-Nov-2017 |
Etienne Carriere <etienne.carriere@linaro.org> |
ARMv7 may not support large page addressing
ARCH_SUPPORTS_LARGE_PAGE_ADDRESSING allows build environment to
handle specific case when target ARMv7 core only supports 32bit MMU
descriptor mode.
If A
ARMv7 may not support large page addressing
ARCH_SUPPORTS_LARGE_PAGE_ADDRESSING allows build environment to
handle specific case when target ARMv7 core only supports 32bit MMU
descriptor mode.
If ARMv7 based platform does not set ARM_CORTEX_Ax=yes, platform
shall define ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING to enable
large page addressing support.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| #
26e63c44 |
| 08-Nov-2017 |
Etienne Carriere <etienne.carriere@linaro.org> |
ARMv7 target is driven by ARM_ARCH_MAJOR==7
External build environment shall sets directive ARM_ARCH_MAJOR to 7
to specify a target ARMv7-A core.
As ARM-TF expects AARCH to be set, ARM_ARCH_MAJOR==
ARMv7 target is driven by ARM_ARCH_MAJOR==7
External build environment shall sets directive ARM_ARCH_MAJOR to 7
to specify a target ARMv7-A core.
As ARM-TF expects AARCH to be set, ARM_ARCH_MAJOR==7 mandates
AARCH=aarch32.
The toolchain target architecture/cpu is delegated after the platform
configuration is parsed. Platform shall define target core through
ARM_CORTEX_A<x>=yes, <x> being 5, 7, 9, 12, 15 and/or 17.
Platform can bypass ARM_CORTEX_A<x>=yes directive and provide straight
the toolchain target directive through MARCH32_DIRECTIVE.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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