Merge "refactor(cpus): don't panic if errata out of order" into integration

chore(cpus): rearrange the errata and cve in order in Cortex-X4

Patch sorts the errata IDs in ascending order and the
CVE's in ascending order based on the year and index
for CPU Cortex-X4.

Change-

chore(cpus): rearrange the errata and cve in order in Cortex-X4

Patch sorts the errata IDs in ascending order and the
CVE's in ascending order based on the year and index
for CPU Cortex-X4.

Change-Id: Ic304c2f68e7d0b96bbb30760696b7bceabe1ae2d
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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chore(cpus): rearrange cve and errata order in Cortex-X3

Patch sorts the errata IDs in ascending order and the
CVE-2024-5660 in order based on the year and index
for Cortex-X3.

Change-Id: I2a4baebe

chore(cpus): rearrange cve and errata order in Cortex-X3

Patch sorts the errata IDs in ascending order and the
CVE-2024-5660 in order based on the year and index
for Cortex-X3.

Change-Id: I2a4baebe0c3133528c089d999bdffa8c992f4989
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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chore(cpus): fix cve order in Neoverse-V2

Patch rearranges CVE-2024-5660 in order based on
the year and index for Neoverse-V2.

Change-Id: I092a93ef3299fd733abae9c462c019f94d881413
Signed-off-by: So

chore(cpus): fix cve order in Neoverse-V2

Patch rearranges CVE-2024-5660 in order based on
the year and index for Neoverse-V2.

Change-Id: I092a93ef3299fd733abae9c462c019f94d881413
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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chore(cpus): rearrange the errata and cve order in Neoverse-N2

Patch sorts the errata IDs in ascending order and the
CVE's in ascending order based on the year and index
for CPU Neoverse N2.

Change

chore(cpus): rearrange the errata and cve order in Neoverse-N2

Patch sorts the errata IDs in ascending order and the
CVE's in ascending order based on the year and index
for CPU Neoverse N2.

Change-Id: Ieb4a8ab0030ea4e83efdef86a0ff1e2990b3e0dd
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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chore(cpus): rearrange the errata and cve in order in Neoverse-V3

Patch sorts the errata IDs in ascending order and the CVE's
in ascending order based on the year and index for Neoverse-V3.

Change-

chore(cpus): rearrange the errata and cve in order in Neoverse-V3

Patch sorts the errata IDs in ascending order and the CVE's
in ascending order based on the year and index for Neoverse-V3.

Change-Id: I108eb2896e24c135d56e5096289766d777b48b48
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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chore(cpus): rearrange the errata and cve in order in Cortex-A710

Patch sorts the errata IDs in ascending order and the
CVE's in ascending order based on the year and index
for CPU Cortex-A710.

Cha

chore(cpus): rearrange the errata and cve in order in Cortex-A710

Patch sorts the errata IDs in ascending order and the
CVE's in ascending order based on the year and index
for CPU Cortex-A710.

Change-Id: Ie7c2b77879f8fa5abb77204678e09cc759b10278
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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chore(cpus): rearrange cve in order in Cortex-X1

Patch rearranges CVE-2024-5660 in ascending order based on
the year and index for Cortex X1.

Change-Id: I0c4206e38f09b1f88ee95e8ce69d7e13b8a9bb2d
Si

chore(cpus): rearrange cve in order in Cortex-X1

Patch rearranges CVE-2024-5660 in ascending order based on
the year and index for Cortex X1.

Change-Id: I0c4206e38f09b1f88ee95e8ce69d7e13b8a9bb2d
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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chore(cpus): fix cve order in Neoverse-V1

This patch rearranges CVE-2024-5660 apply order in Neoverse-V1.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ice0b1c6efa913f885

chore(cpus): fix cve order in Neoverse-V1

This patch rearranges CVE-2024-5660 apply order in Neoverse-V1.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ice0b1c6efa913f88522fb33182b9cdc0e7723988

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chore(cpus): fix cve order in Cortex-X2

This patch rearranges CVE-2024-5660, erratum 2313941
and 3701772 apply order in Cortex-X2.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Chan

chore(cpus): fix cve order in Cortex-X2

This patch rearranges CVE-2024-5660, erratum 2313941
and 3701772 apply order in Cortex-X2.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ie74d7232a14f3cdd14c4d0ffb1ee91b537c491ea

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chore(cpus): fix cve order in Cortex-A78C

This patch rearranges CVE-2024-5660 apply order in Cortex-A78C.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I326be1da279bd34df

chore(cpus): fix cve order in Cortex-A78C

This patch rearranges CVE-2024-5660 apply order in Cortex-A78C.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I326be1da279bd34df8667f7e957fb4a2c6913ab9

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chore(cpus): fix cve order in Cortex-A78_AE

This patch rearranges CVE-2024-5660 apply order in Cortex-A78_AE.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Idfb076b798a84

chore(cpus): fix cve order in Cortex-A78_AE

This patch rearranges CVE-2024-5660 apply order in Cortex-A78_AE.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Idfb076b798a840847c00066bd062ee919369272f

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chore(cpus): fix cve order in Cortex-A78

This patch rearranges CVE-2024-5660 apply order in Cortex-A78.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: If80a0f95f82dbf69100

chore(cpus): fix cve order in Cortex-A78

This patch rearranges CVE-2024-5660 apply order in Cortex-A78.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: If80a0f95f82dbf69100a2687b06db2373a9e9832

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chore(cpus): fix cve order in Cortex-A77

This patch rearranges CVE-2024-5660 apply order in Cortex-A77.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I41d76268ce2248bfd36

chore(cpus): fix cve order in Cortex-A77

This patch rearranges CVE-2024-5660 apply order in Cortex-A77.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I41d76268ce2248bfd3600bbf6b89d16b6bdce8f0

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refactor(cpus): don't panic if errata out of order

Previously we have used enclosed the Errata ordering check
within the FEATURE_DETECTION flag as this flag is only
used for development purpose and

refactor(cpus): don't panic if errata out of order

Previously we have used enclosed the Errata ordering check
within the FEATURE_DETECTION flag as this flag is only
used for development purpose and it also enforces
ordering by causing a panic when the assert fails.
A simple warning message would suffice and hence this
patch removes the assert.

The erratum and cve ordering check is planned to be implemented
in static check at which point the warning will be taken out as well.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I0ffc40361985281163970ea5bc81ca0269b16442

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Merge "fix(plat): remove unused vfp code" into integration

Merge "chore(cm): add MDCR_EL3.RLTE to context management" into integration

Merge "feat(lib): implement strnlen secure and strcpy secure function" into integration

chore(cm): add MDCR_EL3.RLTE to context management

The bit is already implicitly zero so no functional change. Adding it
helps fully describe how we expect FEAT_TRF to behave.

Change-Id: If7a7881e2

chore(cm): add MDCR_EL3.RLTE to context management

The bit is already implicitly zero so no functional change. Adding it
helps fully describe how we expect FEAT_TRF to behave.

Change-Id: If7a7881e2b50188222ce46265b432d658a664c75
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(libc): add const qualifier

This corrects the MISRA violation C2012-8.13:
A pointer should point to a const-qualified type whenever possible.
Added const qualifier to pointer.

In spite of generi

fix(libc): add const qualifier

This corrects the MISRA violation C2012-8.13:
A pointer should point to a const-qualified type whenever possible.
Added const qualifier to pointer.

In spite of generic guidance for 3rd party libraries
(https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html#misra-compliance)
libc contains some MISRA-C fixes done by commit d5ccb754af86
("libc: Fix some MISRA defects") in 2021.
Also from history it is not clear where libc is
coming from that's why there is no way to fix
violation in base library.

Change-Id: I9d6ec6df08358adf0832a53485d080d8b93b0e29
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(plat): remove unused vfp code

The code is never referenced, the build flag is never defined and some
of the #defines are missing. Remove.

Change-Id: I44caae52f9b7503363ac553fd1187bbf6c951438
Si

fix(plat): remove unused vfp code

The code is never referenced, the build flag is never defined and some
of the #defines are missing. Remove.

Change-Id: I44caae52f9b7503363ac553fd1187bbf6c951438
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(lib): implement strnlen secure and strcpy secure function

Implement safer version of 'strnlen' function
to handle NULL terminated strings with additional
bound checking and secure version of st

feat(lib): implement strnlen secure and strcpy secure function

Implement safer version of 'strnlen' function
to handle NULL terminated strings with additional
bound checking and secure version of string copy function
to support better security and avoid destination
buffer overflow.

Change-Id: I93916f003b192c1c6da6a4f78a627c8885db11d9
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>

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Merge "fix(errata): workaround for Cortex-A510 erratum 2971420" into integration

Merge "fix(cpufeat): add feat_hcx check before enabling FEAT_MOPS" into integration

fix(errata): workaround for Cortex-A510 erratum 2971420

Cortex-A510 erratum 2971420 applies to revisions r0p1, r0p2, r0p3,
r1p0, r1p1, r1p2 and r1p3, and is still open.

Under some conditions, data

fix(errata): workaround for Cortex-A510 erratum 2971420

Cortex-A510 erratum 2971420 applies to revisions r0p1, r0p2, r0p3,
r1p0, r1p1, r1p2 and r1p3, and is still open.

Under some conditions, data might be corrupted if Trace Buffer
Extension (TRBE) is enabled. The workaround is to disable trace
collection via TRBE by programming MDCR_EL3.NSTB[1] to the opposite
value of SCR_EL3.NS on a security state switch. Since we only enable
TRBE for non-secure world, the workaround is to disable TRBE by
setting the NSTB field to 00 so accesses are trapped to EL3 and
secure state owns the buffer.

SDEN: https://developer.arm.com/documentation/SDEN-1873361/latest/

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ia77051f6b64c726a8c50596c78f220d323ab7d97

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