| f8872c94 | 12-Dec-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(cpus): workaround for Cortex-X4 erratum 2923985" into integration |
| a57e18e4 | 11-Nov-2024 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
feat(fpmr): disable FPMR trap
This patch enables support of FEAT_FPMR by enabling access to FPMR register. It achieves it by setting the EnFPM bit of SCR_EL3. This feature is currently enabled for N
feat(fpmr): disable FPMR trap
This patch enables support of FEAT_FPMR by enabling access to FPMR register. It achieves it by setting the EnFPM bit of SCR_EL3. This feature is currently enabled for NS world only.
Reference: https://developer.arm.com/documentation/109697/2024_09/ Feature-descriptions/The-Armv9-5-architecture-extension?lang=en
Change-Id: I580c409b9b22f8ead0737502280fb9093a3d5dd2 Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
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| cc461661 | 27-Nov-2024 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
fix(cpus): workaround for Cortex-X4 erratum 2923985
Cortex-X4 erratum 2923935 is a Cat B erratum that applies to all revisions <= r0p1 and is fixed in r0p2.
The workaround is to set CPUACTLR4_EL1[1
fix(cpus): workaround for Cortex-X4 erratum 2923985
Cortex-X4 erratum 2923935 is a Cat B erratum that applies to all revisions <= r0p1 and is fixed in r0p2.
The workaround is to set CPUACTLR4_EL1[11:10] to 0b11.
SDEN documentation: https://developer.arm.com/documentation/SDEN-2432808/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Change-Id: I9207802ad479919a7f77c1271019fa2479e076ee
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| e372c291 | 11-Dec-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "chore(romlib): remove unused jmptbl.i file" into integration |
| 8953568a | 13-May-2024 |
Levi Yun <yeoreum.yun@arm.com> |
feat(lib): introduce Hob creation library
According to Platform Initialization (PI) Specification [1] and discussion on edk2 mailing list [2], StandaloneMm shouldn't create Hob but it should be pass
feat(lib): introduce Hob creation library
According to Platform Initialization (PI) Specification [1] and discussion on edk2 mailing list [2], StandaloneMm shouldn't create Hob but it should be passed from TF-A. IOW, TF-A should pass boot information via HOB list to initialise StandaloneMm properly.
And this HOB lists could be delivered via - SPM_MM: Transfer List according to the firmware handoff spec[3]
- FF-A v1.1 >= : FF-A boot protocol.
This patch introduces a TF-A HOB creation library and some of definitions which StandaloneMm requires to boot.
Link: https://uefi.org/sites/default/files/resources/PI_Spec_1_6.pdf [1] Link: https://edk2.groups.io/g/devel/topic/103675962#114283 [2] Link: https://github.com/FirmwareHandoff/firmware_handoff [3] Signed-off-by: Levi Yun <yeoreum.yun@arm.com> Change-Id: I5e0838adce487110206998a8b79bc3adca922cec
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| 6b68b4a4 | 13-May-2024 |
Levi Yun <yeoreum.yun@arm.com> |
feat(lib): modify Hob creation code imported from edk2
According to Platform Initialization (PI) Specification [1] and Discussion on edk2 mailing list [2], StandaloneMm shouldn't create Hob but it s
feat(lib): modify Hob creation code imported from edk2
According to Platform Initialization (PI) Specification [1] and Discussion on edk2 mailing list [2], StandaloneMm shouldn't create Hob but it should be passed from TF-A. IOW, TF-A should pass boot information via PHIT Hob to initialize StandaloneMm properly.
This patch modifies Hob creation code from edk2 codebase so that TF-A could create Hob information properly to boot StandaloneMm
Link: https://uefi.org/sites/default/files/resources/PI_Spec_1_6.pdf [1] Link: https://edk2.groups.io/g/devel/topic/103675962#114283 [2] Signed-off-by: Levi Yun <yeoreum.yun@arm.com> Change-Id: I5e427b620d8006b118b266370bd08d4b0ff56a83
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| 21058318 | 23-Sep-2024 |
Levi Yun <yeoreum.yun@arm.com> |
feat(lib): copy StandaloneMm Hob creation library in edk2
According to Platform Initialization (PI) Specification [1] and Discussion on edk2 mailing list [2], StandaloneMm shouldn't create Hob but i
feat(lib): copy StandaloneMm Hob creation library in edk2
According to Platform Initialization (PI) Specification [1] and Discussion on edk2 mailing list [2], StandaloneMm shouldn't create Hob but it should be passed from TF-A. IOW, TF-A should pass boot information via PHIT Hob to initialise StandaloneMm properly.
To create Hob information to boot StandaloneMm, copy Hob creation code form edk2 codebase: https://github.com/tianocore/edk2/blob/master/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/Arm/StandaloneMmCoreHobLib.c
Link: https://uefi.org/sites/default/files/resources/PI_Spec_1_6.pdf [1] Link: https://edk2.groups.io/g/devel/topic/103675962#114283 [2] Signed-off-by: Levi Yun <yeoreum.yun@arm.com> Change-Id: I784684d63f21a7879a2438ed522e158ca785186e
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| e4a070e3 | 03-Dec-2024 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
fix(romlib): romlib build without MbedTLS
The ROMLIB build currently has a strong dependency on MbedTLS. This patch has been introduced to remove this dependency, making it more flexible.
Change-Id
fix(romlib): romlib build without MbedTLS
The ROMLIB build currently has a strong dependency on MbedTLS. This patch has been introduced to remove this dependency, making it more flexible.
Change-Id: If8c4cc7cf557687f40b235a4b8f931cfb70943fd Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 13a1ec38 | 05-Dec-2024 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
chore(romlib): remove unused jmptbl.i file
Remove the unused jmptbl.i file. The ROMLIB Makefile expects platforms to provide the jmptbl according to their requirements.
Change-Id: I2784eaca5061aa77
chore(romlib): remove unused jmptbl.i file
Remove the unused jmptbl.i file. The ROMLIB Makefile expects platforms to provide the jmptbl according to their requirements.
Change-Id: I2784eaca5061aa77fdd99f7b2b5ef5a1145475e9 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 940ecd07 | 29-Nov-2024 |
Igor Podgainõi <igor.podgainoi@arm.com> |
feat(cpus): add support for Alto CPU
Add basic CPU library code to support the Alto CPU.
Change-Id: I45958be99c4a350a32a9e511d3705fb568b97236 Signed-off-by: Igor Podgainõi <igor.podgainoi@arm.com> |
| 6e622818 | 03-Sep-2024 |
Chris Kay <chris.kay@arm.com> |
build: use full paths for generated libraries
This change modifies the build rules for static libraries so that individual rules which use those libraries depend directly on the archive files that a
build: use full paths for generated libraries
This change modifies the build rules for static libraries so that individual rules which use those libraries depend directly on the archive files that are generated, rather than their phony target aliases and `-lX` link flags.
The goal of this is to clean up Make's view of the dependencies between files, avoiding phony targets (which do not honour timestamps) making their way into intermediate dependencies.
Change-Id: I96d655fcd94dc259ffa6e8970b2be7b8c7e11123 Signed-off-by: Chris Kay <chris.kay@arm.com>
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| 212993ae | 06-Nov-2024 |
Govindraj Raja <govindraj.raja@arm.com> |
Merge "feat(cpufeat): add ENABLE_FEAT_LS64_ACCDATA" into integration |
| ffbc2b90 | 06-Nov-2024 |
Yann Gautier <yann.gautier@st.com> |
Merge "fix(romlib): prevent race condition on the build directory" into integration |
| 19d52a83 | 09-Aug-2024 |
Andre Przywara <andre.przywara@arm.com> |
feat(cpufeat): add ENABLE_FEAT_LS64_ACCDATA
Armv8.6 introduced the FEAT_LS64 extension, which provides a 64 *byte* store instruction. A related instruction is ST64BV0, which will replace the lowest
feat(cpufeat): add ENABLE_FEAT_LS64_ACCDATA
Armv8.6 introduced the FEAT_LS64 extension, which provides a 64 *byte* store instruction. A related instruction is ST64BV0, which will replace the lowest 32 bits of the data with a value taken from the ACCDATA_EL1 system register (so that EL0 cannot alter them). Using that ST64BV0 instruction and accessing the ACCDATA_EL1 system register is guarded by two SCR_EL3 bits, which we should set to avoid a trap into EL3, when lower ELs use one of those.
Add the required bits and pieces to make this feature usable: - Add the ENABLE_FEAT_LS64_ACCDATA build option (defaulting to 0). - Add the CPUID and SCR_EL3 bit definitions associated with FEAT_LS64. - Add a feature check to check for the existing four variants of the LS64 feature and detect future extensions. - Add code to save and restore the ACCDATA_EL1 register on secure/non-secure context switches. - Enable the feature with runtime detection for FVP and Arm FPGA.
Please note that the *basic* FEAT_LS64 feature does not feature any trap bits, it's only the addition of the ACCDATA_EL1 system register that adds these traps and the SCR_EL3 bits.
Change-Id: Ie3e2ca2d9c4fbbd45c0cc6089accbb825579138a Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| 830ed392 | 05-Nov-2024 |
Govindraj Raja <govindraj.raja@arm.com> |
Merge "feat(feat_sctlr2): enable FEAT_SCTLR2 for Realm world" into integration |
| b17fecd6 | 28-Oct-2024 |
Javier Almansa Sobrino <javier.almansasobrino@arm.com> |
feat(feat_sctlr2): enable FEAT_SCTLR2 for Realm world
Change-Id: I62e769ae796bbeb41741c2c421a5f129d875f5fb Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> |
| e01bcfb0 | 04-Nov-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "build: fix grouped targets on Make <= 4.2" into integration |
| 25cde5f8 | 30-Oct-2024 |
Boyan Karatotev <boyan.karatotev@arm.com> |
fix(romlib): prevent race condition on the build directory
When building with many cores (-j64), there's a good chance that the rule to make the build directory is getting executed at the same time
fix(romlib): prevent race condition on the build directory
When building with many cores (-j64), there's a good chance that the rule to make the build directory is getting executed at the same time as the rule for romlib.ldflags. On my machine, the former is slower, resulting in romlib_generator.py not being able to write the file as the directory doesn't exist yet.
Add an explicit dependency on the build directory for the target. This ensures that we have a build directory before we start putting stuff in it.
Change-Id: I120b0dc66c692c759ab1046c735be405b41db87c Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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| a57b94ec | 06-Aug-2024 |
Chris Kay <chris.kay@arm.com> |
build: fix grouped targets on Make <= 4.2
Grouped targets are a feature introduced with GNU Make 4.3 which enable rules with multiple targets to communicate that all of the targets of that rule are
build: fix grouped targets on Make <= 4.2
Grouped targets are a feature introduced with GNU Make 4.3 which enable rules with multiple targets to communicate that all of the targets of that rule are built simultaneously, rather than independently.
For example, without grouped targets the following rule may be executed twice:
a.txt b.txt: touch a.txt b.txt
# $ remake -j2 a.txt b.txt # touch a.txt b.txt # touch a.txt b.txt
In this example, both `a.txt` and `b.txt` are touched twice, when the rule should only be executed once. Instead, this rule can use a grouped target:
a.txt b.txt &: touch a.txt b.txt
# $ remake -j2 a.txt b.txt # touch a.txt b.txt # remake: 'b.txt' is up to date.
In this case, both `a.txt` and `b.txt` are created once only, as Make now knows that the recipe will create both files.
Note that pattern rules with multiple targets always behave this way.
Previously, we assumed that the grouped target feature was available, but on systems still packaging Make 4.2, most prominently Ubuntu 20.04, this is not the case. This change adds a check to ensure that we do not use grouped targets if they are unavailable.
Change-Id: Ifd9da35421ae11468d7a25d3cbc76f6036921749 Signed-off-by: Chris Kay <chris.kay@arm.com>
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| 30655136 | 06-Sep-2024 |
Govindraj Raja <govindraj.raja@arm.com> |
feat(d128): add support for FEAT_D128
This patch disables trapping to EL3 when the FEAT_D128 specific registers are accessed by setting the SCR_EL3.D128En bit.
If FEAT_D128 is implemented, then FEA
feat(d128): add support for FEAT_D128
This patch disables trapping to EL3 when the FEAT_D128 specific registers are accessed by setting the SCR_EL3.D128En bit.
If FEAT_D128 is implemented, then FEAT_SYSREG128 is implemented. With FEAT_SYSREG128 certain system registers are treated as 128-bit, so we should be context saving and restoring 128-bits instead of 64-bit when FEAT_D128 is enabled.
FEAT_SYSREG128 adds support for MRRS and MSRR instruction which helps us to read write to 128-bit system register. Refer to Arm Architecture Manual for further details.
Change the FVP platform to default to handling this as a dynamic option so the right decision can be made by the code at runtime.
Change-Id: I1a53db5eac29e56c8fbdcd4961ede3abfcb2411a Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| 190ae702 | 24-Oct-2024 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "feat(cpus): add support for cortex-a720ae" into integration |
| 034b9197 | 21-Oct-2024 |
Govindraj Raja <govindraj.raja@arm.com> |
Merge "chore(cpus): optimise runtime errata applications" into integration |
| 2752c2a8 | 21-Oct-2024 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "feat(cpus): add support for arcadia cpu" into integration |
| 8118078b | 15-Oct-2024 |
Ahmed Azeem <ahmed.azeem@arm.com> |
feat(cpus): add support for cortex-a720ae
Add the basic CPU library code to support Cortex-A720AE. The overall library code is adapted based on Cortex-A720 code.
Signed-off-by: David Hu <david.hu2@
feat(cpus): add support for cortex-a720ae
Add the basic CPU library code to support Cortex-A720AE. The overall library code is adapted based on Cortex-A720 code.
Signed-off-by: David Hu <david.hu2@arm.com> Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com> Change-Id: I3d64dc5a3098cc823e656a5ad3ea05cd71598dc6
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| 5ec9ade9 | 21-Oct-2024 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "fix(brbe): allow RME builds with BRBE" into integration |