| bbb24f61 | 21-May-2019 |
John Tsichritzis <john.tsichritzis@arm.com> |
Introduce BTI support in ROMLIB
When TF-A is compiled with BTI enabled, the branches in the ROMLIB
jumptable must be preceded by a "bti j" instruction.
Moreover, when the additional "bti" instructi
Introduce BTI support in ROMLIB
When TF-A is compiled with BTI enabled, the branches in the ROMLIB
jumptable must be preceded by a "bti j" instruction.
Moreover, when the additional "bti" instruction is inserted, the
jumptable entries have a distance of 8 bytes between them instead of 4.
Hence, the wrappers are also modified accordinly.
If TF-A is compiled without BTI enabled, the ROMLIB jumptable and
wrappers are generated as before.
Change-Id: Iaa59897668f8e59888d39046233300c2241d8de7
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
show more ...
|
| 2b929c98 | 29-Apr-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
romlib: Improve compilation flags definition
* Optimization flags were only provided for debug build.
* Set optimisation level to -O1
* Remove CFLAGS which is never used for romlib
* Remove the igno
romlib: Improve compilation flags definition
* Optimization flags were only provided for debug build.
* Set optimisation level to -O1
* Remove CFLAGS which is never used for romlib
* Remove the ignored -g flag from LDFLAGS
Change-Id: Id4b69026d8a322ed4cb0acf06c350f13d31571ad
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
show more ...
|
| 482fc9c8 | 16-May-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "sami/550_fix_n1sdp_issues_v1" into integration
* changes:
N1SDP: Initialise CNTFRQ in Non Secure CNTBaseN
N1SDP: Fix DRAM2 start address
Add option for defining platf
Merge changes from topic "sami/550_fix_n1sdp_issues_v1" into integration
* changes:
N1SDP: Initialise CNTFRQ in Non Secure CNTBaseN
N1SDP: Fix DRAM2 start address
Add option for defining platform DRAM2 base
Disable speculative loads only if SSBS is supported
show more ...
|
| eca6e453 | 10-May-2019 |
Sami Mujawar <sami.mujawar@arm.com> |
Disable speculative loads only if SSBS is supported
Examine the ID_AA64PFR1_EL1 bits 7:4 to see if speculative
loads (SSBS) is implemented, before disabling speculative
loads.
Change-Id: I7607c45ed
Disable speculative loads only if SSBS is supported
Examine the ID_AA64PFR1_EL1 bits 7:4 to see if speculative
loads (SSBS) is implemented, before disabling speculative
loads.
Change-Id: I7607c45ed2889260d22a94f6fd9af804520acf67
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
show more ...
|
| 02a85c11 | 10-May-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Remove .arch directives from spinlock.S
This patch removes .arch "arm8.1-a" and "armv8-a"
directives which overwrite ASFLAGS_aarch64 option based
on ARM_ARCH_MINOR passed to Makefile and cause
trans
Remove .arch directives from spinlock.S
This patch removes .arch "arm8.1-a" and "armv8-a"
directives which overwrite ASFLAGS_aarch64 option based
on ARM_ARCH_MINOR passed to Makefile and cause
translation errors like
"selected processor does not support `bti jc'"
for armv8.5-a targets when BTI support is enabled.
Change-Id: Idca5b66ed1e5d86e2188b0c0f16c3819990957c4
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
show more ...
|
| 0cdbd023 | 07-May-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "sm/fix_a76_errata" into integration
* changes:
Workaround for cortex-A76 errata 1286807
Cortex-A76: workarounds for errata 1257314, 1262606, 1262888, 1275112 |
| f85edcea | 03-May-2019 |
Soby Mathew <soby.mathew@arm.com> |
Workaround for cortex-A76 errata 1286807
The workaround for Cortex-A76 errata #1286807 is implemented
in this patch.
Change-Id: I6c15af962ac99ce223e009f6d299cefb41043bed
Signed-off-by: Soby Mathew
Workaround for cortex-A76 errata 1286807
The workaround for Cortex-A76 errata #1286807 is implemented
in this patch.
Change-Id: I6c15af962ac99ce223e009f6d299cefb41043bed
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
show more ...
|
| e6e1d0ac | 01-May-2019 |
Soby Mathew <soby.mathew@arm.com> |
Cortex-A76: workarounds for errata 1257314, 1262606, 1262888, 1275112
The workarounds for errata 1257314, 1262606, 1262888 and 1275112 are
added to the Cortex-A76 cpu specific file. The workarounds
Cortex-A76: workarounds for errata 1257314, 1262606, 1262888, 1275112
The workarounds for errata 1257314, 1262606, 1262888 and 1275112 are
added to the Cortex-A76 cpu specific file. The workarounds are disabled
by default and have to be explicitly enabled by the platform integrator.
Change-Id: I70474927374cb67725f829d159ddde9ac4edc343
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
show more ...
|
| 076b5f02 | 19-Mar-2019 |
John Tsichritzis <john.tsichritzis@arm.com> |
Add compile-time errors for HW_ASSISTED_COHERENCY flag
This patch fixes this issue:
https://github.com/ARM-software/tf-issues/issues/660
The introduced changes are the following:
1) Some cores imp
Add compile-time errors for HW_ASSISTED_COHERENCY flag
This patch fixes this issue:
https://github.com/ARM-software/tf-issues/issues/660
The introduced changes are the following:
1) Some cores implement cache coherency maintenance operation on the
hardware level. For those cores, such as - but not only - the DynamIQ
cores, it is mandatory that TF-A is compiled with the
HW_ASSISTED_COHERENCY flag. If not, the core behaviour at runtime is
unpredictable. To prevent this, compile time checks have been added and
compilation errors are generated, if needed.
2) To enable this change for FVP, a logical separation has been done for
the core libraries. A system cannot contain cores of both groups, i.e.
cores that manage coherency on hardware and cores that don't do it. As
such, depending on the HW_ASSISTED_COHERENCY flag, FVP includes the
libraries only of the relevant cores.
3) The neoverse_e1.S file has been added to the FVP sources.
Change-Id: I787d15819b2add4ec0d238249e04bf0497dc12f3
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
show more ...
|
| 29162843 | 30-Apr-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "lm/stack_protector" into integration
* changes:
juno: Add security sources for tsp-juno
Add support for default stack-protector flag |
| fd7b287c | 26-Mar-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
Add support for default stack-protector flag
The current stack-protector support is for none, "strong" or "all".
The default use of the flag enables the stack-protection to all
functions that declar
Add support for default stack-protector flag
The current stack-protector support is for none, "strong" or "all".
The default use of the flag enables the stack-protection to all
functions that declare a character array of eight bytes or more in
length on their stack.
This option can be tuned with the --param=ssp-buffer-size=N option.
Change-Id: I11ad9568187d58de1b962b8ae04edd1dc8578fb0
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
show more ...
|
| cd884aa6 | 24-Apr-2019 |
Andrew F. Davis <afd@ti.com> |
Cortex-A53: Fix reporting of missing errata when not needed
Errata 819472, 824069, and 827319 are currently reported in a warning as
missing during boot for platforms that do not need them. Only war
Cortex-A53: Fix reporting of missing errata when not needed
Errata 819472, 824069, and 827319 are currently reported in a warning as
missing during boot for platforms that do not need them. Only warn when
the errata is needed for a given revision but not compiled in like other
errata workarounds.
Fixes: bd393704d2b1 ("Cortex-A53: Workarounds for 819472, 824069 and 827319")
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Ifd757b3d0e73a9bd465b98dc20648b6c13397d8d
show more ...
|
| 632ab3eb | 18-Apr-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
Neoverse N1: Forces cacheable atomic to near
This patch forces all cacheable atomic instructions to be near, which
improves performance in highly contended parallelized use-cases.
Change-Id: I93fac
Neoverse N1: Forces cacheable atomic to near
This patch forces all cacheable atomic instructions to be near, which
improves performance in highly contended parallelized use-cases.
Change-Id: I93fac62847f4af8d5eaaf3b52318c30893e947d3
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
show more ...
|
| 0e985d70 | 09-Apr-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
DSU: Implement workaround for errata 798953
Under certain near idle conditions, DSU may miss response transfers on
the ACE master or Peripheral port, leading to deadlock. This workaround
disables hi
DSU: Implement workaround for errata 798953
Under certain near idle conditions, DSU may miss response transfers on
the ACE master or Peripheral port, leading to deadlock. This workaround
disables high-level clock gating of the DSU to prevent this.
Change-Id: I820911d61570bacb38dd325b3519bc8d12caa14b
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
show more ...
|
| 2c3b76ce | 09-Apr-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
DSU: Small fix and reformat on errata framework
Change-Id: I50708f6ccc33059fbfe6d36fd66351f0b894311f
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> |
| cba71b70 | 05-Apr-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
Cortex-A35: Implement workaround for errata 855472
Under specific conditions, the processor might issue an eviction and an
L2 cache clean operation to the interconnect in the wrong order. Set
the CP
Cortex-A35: Implement workaround for errata 855472
Under specific conditions, the processor might issue an eviction and an
L2 cache clean operation to the interconnect in the wrong order. Set
the CPUACTLR.ENDCCASCI bit to 1 to avoid this.
Change-Id: Ide7393adeae04581fa70eb9173b742049fc3e050
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
show more ...
|
| dd4cf2c7 | 10-Apr-2019 |
Joel Hutton <Joel.Hutton@arm.com> |
Cortex A9:errata 794073 workaround
On Cortex A9 an errata can cause the processor to violate the rules for
speculative fetches when the MMU is off but branch prediction has not
been disabled. The wo
Cortex A9:errata 794073 workaround
On Cortex A9 an errata can cause the processor to violate the rules for
speculative fetches when the MMU is off but branch prediction has not
been disabled. The workaround for this is to execute an Invalidate
Entire Branch Prediction Array (BPIALL) followed by a DSB.
see:http://arminfo.emea.arm.com/help/topic/com.arm.doc.uan0009d/UAN0009_cortex_a9_errata_r4.pdf
for more details.
Change-Id: I9146c1fa7563a79f4e15b6251617b9620a587c93
Signed-off-by: Joel Hutton <Joel.Hutton@arm.com>
show more ...
|
| c554e1ad | 09-Apr-2019 |
Joel Hutton <Joel.Hutton@Arm.com> |
cache_helpers.s:fix mixed tabs and spaces
Change-Id: I8b7c7888d09200410e1a1c11a070c94dd8013ea7
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com> |
| f999faca | 09-Apr-2019 |
Joel Hutton <Joel.Hutton@Arm.com> |
Add note about erratum 814220 for A7
On Cortex-A7 an L2 set/way cache maintenance operation can overtake
an L1 set/way cache maintenance operation. The mitigation for this is
to use a `DSB` instruct
Add note about erratum 814220 for A7
On Cortex-A7 an L2 set/way cache maintenance operation can overtake
an L1 set/way cache maintenance operation. The mitigation for this is
to use a `DSB` instruction before changing cache. The cache cleaning
code happens to already be doing this, so only a comment was added.
Change-Id: Ia1ffb8ca8b6bbbba422ed6f6818671ef9fe02d90
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
show more ...
|
| 9ccc5a57 | 04-Apr-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Add support for Cortex-A76AE CPU
Change-Id: I0a81f4ea94d41245cd5150de341b51fc70babffe
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> |
| c6cafcd7 | 27-Mar-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Remove deprecated interfaces
Change-Id: I14fcabbdfd53153d1d5f187f6f8b23a045794408
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> |
| 6de6965b | 27-Mar-2019 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
SPM: Move shim layer to TTBR1_EL1
This gives each Secure Partition complete freedom on its address space.
Previously, the memory used by the exception vectors was reserved and
couldn't be used. Also
SPM: Move shim layer to TTBR1_EL1
This gives each Secure Partition complete freedom on its address space.
Previously, the memory used by the exception vectors was reserved and
couldn't be used. Also, it always had to be mapped, forcing SPM to
generate translation tables that included the exception vectors as well
as the Partition memory regions. With this change, partitions can reduce
their address space size easily.
Change-Id: I67fb5e9bdf2870b73347f23bff702fab0a8f8711
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
show more ...
|
| bde2836f | 14-Feb-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Remove several warnings reported with W=2
Improved support for W=2 compilation flag by solving some nested-extern
and sign-compare warnings.
The libraries are compiling with warnings (which turn in
Remove several warnings reported with W=2
Improved support for W=2 compilation flag by solving some nested-extern
and sign-compare warnings.
The libraries are compiling with warnings (which turn into errors with
the Werror flag).
Outside of libraries, some warnings cannot be fixed.
Change-Id: I06b1923857f2a6a50e93d62d0274915b268cef05
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
show more ...
|
| 609e053c | 13-Feb-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Remove several warnings reported with W=1
Improved support for W=1 compilation flag by solving missing-prototypes
and old-style-definition warnings.
The libraries are compiling with warnings (which
Remove several warnings reported with W=1
Improved support for W=1 compilation flag by solving missing-prototypes
and old-style-definition warnings.
The libraries are compiling with warnings (which turn into errors with
the Werror flag).
Outside of libraries, some warnings cannot be fixed without heavy
structural changes.
Change-Id: I1668cf99123ac4195c2a6a1d48945f7a64c67f16
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
show more ...
|
| 46d58f80 | 21-Mar-2019 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1902 from jts-arm/romlib
ROMLIB bug fixes |