| #
df22d602 |
| 14-Apr-2016 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Add support for Cortex-A57 erratum 826974 workaround
Change-Id: I45641551474f4c58c638aff8c42c0ab9a8ec78b4
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| #
097b787a |
| 14-Apr-2016 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Fix wording in cpu-ops.mk comments
The CPU errata build flags don't enable errata, they enable errata
workarounds.
Change-Id: Ica65689d1205fc54eee9081a73442144b973400f
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| #
60616047 |
| 09-Feb-2016 |
danh-arm <dan.handley@arm.com> |
Merge pull request #514 from sandrine-bailleux/sb/a53-a57-disable-non-temporal-hint
Disable non-temporal hint on Cortex-A53/57
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| #
54035fc4 |
| 13-Jan-2016 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Disable non-temporal hint on Cortex-A53/57
The LDNP/STNP instructions as implemented on Cortex-A53 and
Cortex-A57 do not behave in a way most programmers expect, and will
most probably result in a s
Disable non-temporal hint on Cortex-A53/57
The LDNP/STNP instructions as implemented on Cortex-A53 and
Cortex-A57 do not behave in a way most programmers expect, and will
most probably result in a significant speed degradation to any code
that employs them. The ARMv8-A architecture (see Document ARM DDI
0487A.h, section D3.4.3) allows cores to ignore the non-temporal hint
and treat LDNP/STNP as LDP/STP instead.
This patch introduces 2 new build flags:
A53_DISABLE_NON_TEMPORAL_HINT and A57_DISABLE_NON_TEMPORAL_HINT
to enforce this behaviour on Cortex-A53 and Cortex-A57. They are
enabled by default.
The string printed in debug builds when a specific CPU errata
workaround is compiled in but skipped at runtime has been
generalised, so that it can be reused for the non-temporal hint use
case as well.
Change-Id: I3e354f4797fd5d3959872a678e160322b13867a1
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| #
aaa0567c |
| 11-Aug-2015 |
danh-arm <dan.handley@arm.com> |
Merge pull request #356 from mtk09422/mt8173-support-v3
Mt8173 support v3
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| #
6b0d97b2 |
| 29-Jul-2015 |
Jimmy Huang <jimmy.huang@mediatek.com> |
cortex_a53: Add A53 errata #826319, #836870
- Apply a53 errata #826319 to revision <= r0p2
- Apply a53 errata #836870 to revision <= r0p3
- Update docs/cpu-specific-build-macros.md for newly added e
cortex_a53: Add A53 errata #826319, #836870
- Apply a53 errata #826319 to revision <= r0p2
- Apply a53 errata #836870 to revision <= r0p3
- Update docs/cpu-specific-build-macros.md for newly added errata build flags
Change-Id: I44918e36b47dca1fa29695b68700ff9bf888865e
Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
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| #
82b9b297 |
| 30-Oct-2014 |
danh-arm <dan.handley@arm.com> |
Merge pull request #218 from soby-mathew/sm/add_cpu_ops_warning
Add level specific cache operations and changes to errata workaround mechanism
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| #
5541bb3f |
| 22-Sep-2014 |
Soby Mathew <soby.mathew@arm.com> |
Optimize Cortex-A57 cluster power down sequence on Juno
This patch optimizes the Cortex-A57 cluster power down sequence by not
flushing the Level1 data cache. The L1 data cache and the L2 unified
ca
Optimize Cortex-A57 cluster power down sequence on Juno
This patch optimizes the Cortex-A57 cluster power down sequence by not
flushing the Level1 data cache. The L1 data cache and the L2 unified
cache are inclusive. A flush of the L2 by set/way flushes any dirty
lines from the L1 as well. This is a known safe deviation from the
Cortex-A57 TRM defined power down sequence. This optimization can be
enabled by the platform through the 'SKIP_A57_L1_FLUSH_PWR_DWN' build
flag. Each Cortex-A57 based platform must make its own decision on
whether to use the optimization.
This patch also renames the cpu-errata-workarounds.md to
cpu-specific-build-macros.md as this facilitates documentation
of both CPU Specific errata and CPU Specific Optimization
build macros.
Change-Id: I299b9fe79e9a7e08e8a0dffb7d345f9a00a71480
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