| #
75a1ada9 |
| 04-Mar-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Cortex-A15: Implement workaround for errata 816470
Change-Id: I9755252725be25bfd0147839d7df56888424ff84
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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| #
37118a1b |
| 01-Mar-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1849 from loumay-arm/lm/a73_errata
Cortex-A73: Implement workaround for errata 852427
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| #
4476838a |
| 01-Mar-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1845 from ambroise-arm/av/errata
Apply workarounds for errata of Cortex-A53, A55 and A57
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| #
25278eab |
| 27-Feb-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
Cortex-A73: Implement workaround for errata 852427
In AArch32, execution of 2 instructions with opposite condition code
might lead to either a data corruption or a CPU deadlock. Set the bit
12 of th
Cortex-A73: Implement workaround for errata 852427
In AArch32, execution of 2 instructions with opposite condition code
might lead to either a data corruption or a CPU deadlock. Set the bit
12 of the Diagnostic Register to prevent this.
Change-Id: I22b4f25fe933e2942fd785e411e7c0aa39d5c1f4
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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| #
64503b2f |
| 28-Feb-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1839 from loumay-arm/lm/a7x_errata
Cortex-A73/75/76 errata workaround
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| #
bd393704 |
| 21-Feb-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Cortex-A53: Workarounds for 819472, 824069 and 827319
The workarounds for these errata are so closely related that it is
better to only have one patch to make it easier to understand.
Change-Id: I0
Cortex-A53: Workarounds for 819472, 824069 and 827319
The workarounds for these errata are so closely related that it is
better to only have one patch to make it easier to understand.
Change-Id: I0287fa69aefa8b72f884833f6ed0e7775ca834e9
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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| #
5bd2c24f |
| 21-Feb-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Cortex-A57: Implement workaround for erratum 817169
Change-Id: I25f29a275ecccd7d0c9d33906e6c85967caa767a
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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| #
0f6fbbd2 |
| 21-Feb-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Cortex-A57: Implement workaround for erratum 814670
Change-Id: Ice3dcba8c46cea070fd4ca3ffb32aedc840589ad
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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| #
47949f3f |
| 21-Feb-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Cortex-A55: Implement workaround for erratum 903758
Change-Id: I07e69061ba7a918cdfaaa83fa3a42dee910887d7
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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| #
6e78973e |
| 21-Feb-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Cortex-A55: Implement workaround for erratum 846532
Change-Id: Iacb6331c1f6b27340e71279f92f147ebbc71862f
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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| #
6ab87d29 |
| 21-Feb-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Cortex-A55: Implement workaround for erratum 798797
Change-Id: Ic42b37b8500d5e592af2b9fe130f35a0e2db4d14
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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| #
a6cc6610 |
| 21-Feb-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Cortex-A55: Implement workaround for erratum 778703
Change-Id: I094e5cb2c44618e7a4116af5fbb6b18078a79951
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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| #
1afeee92 |
| 21-Feb-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Cortex-A55: Implement workaround for erratum 768277
Change-Id: Iebd45ef5e39ee7080235fb85414ce5b2e776f90c
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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| #
5c6aa01a |
| 25-Feb-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
Add workaround for errata 1073348 for Cortex-A76
Concurrent instruction TLB miss and mispredicted return instruction
might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to
prevent this.
Add workaround for errata 1073348 for Cortex-A76
Concurrent instruction TLB miss and mispredicted return instruction
might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to
prevent this.
Change-Id: I2da4f30cd2df3f5e885dd3c4825c557492d1ac58
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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|
| #
5cc8c7ba |
| 25-Feb-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
Add workaround for errata 1220197 for Cortex-A76
Streaming store under specific conditions might cause deadlock or data
corruption. Set bit 25:24 of CPUECTLR_EL1, which disables write
streaming to t
Add workaround for errata 1220197 for Cortex-A76
Streaming store under specific conditions might cause deadlock or data
corruption. Set bit 25:24 of CPUECTLR_EL1, which disables write
streaming to the L2 to prevent this.
Change-Id: Ib5cabb997b35ada78b27e75787afd610ea606dcf
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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| #
508d7110 |
| 21-Feb-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
Add workaround for errata 1130799 for Cortex-A76
TLBI VAAE1 or TLBI VAALE1 targeting a page within hardware page
aggregated address translation data in the L2 TLB might cause
corruption of address t
Add workaround for errata 1130799 for Cortex-A76
TLBI VAAE1 or TLBI VAALE1 targeting a page within hardware page
aggregated address translation data in the L2 TLB might cause
corruption of address translation data. Set bit 59 of CPUACTLR2_EL1 to
prevent this.
Change-Id: I59f3edea54e87d264e0794f5ca2a8c68a636e586
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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| #
98551591 |
| 25-Feb-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
Add workaround for errata 790748 for Cortex-A75
Internal timing conditions might cause the CPU to stop processing
interrupts. Set bit 13 of CPUACTLR_EL1 to prevent this.
Change-Id: Ifdd19dbcdb71bb0
Add workaround for errata 790748 for Cortex-A75
Internal timing conditions might cause the CPU to stop processing
interrupts. Set bit 13 of CPUACTLR_EL1 to prevent this.
Change-Id: Ifdd19dbcdb71bb0d9609cab1315c478aaedb03ba
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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|
| #
5f5d1ed7 |
| 20-Feb-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
Add workaround for errata 764081 of Cortex-A75
Implicit Error Synchronization Barrier (IESB) might not be correctly
generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all
expection l
Add workaround for errata 764081 of Cortex-A75
Implicit Error Synchronization Barrier (IESB) might not be correctly
generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all
expection levels.
Change-Id: I2a1a568668a31e4f3f38d0fba1d632ad9939e5ad
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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|
| #
e6cab15d |
| 21-Feb-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
Add workaround for errata 855423 of Cortex-A73
Broadcast maintainance operations might not be correctly synchronized
between cores. Set bit 7 of S3_0_C15_C0_2 to prevent this.
Change-Id: I67fb62c0b
Add workaround for errata 855423 of Cortex-A73
Broadcast maintainance operations might not be correctly synchronized
between cores. Set bit 7 of S3_0_C15_C0_2 to prevent this.
Change-Id: I67fb62c0b458d44320ebaedafcb8495ff26c814b
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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|
| #
3f995f30 |
| 22-Feb-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1835 from jts-arm/rename
Apply official names to new Arm Neoverse cores
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| #
da6d75a0 |
| 19-Feb-2019 |
John Tsichritzis <john.tsichritzis@arm.com> |
Rename Cortex-Ares to Neoverse N1
Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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| #
f147a8f8 |
| 20-Aug-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1523 from jts-arm/dsu
DSU erratum 936184 workaround
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| #
8a677180 |
| 23-Jul-2018 |
John Tsichritzis <john.tsichritzis@arm.com> |
DSU erratum 936184 workaround
If the system is in near idle conditions, this erratum could cause a
deadlock or data corruption. This patch applies the workaround that
prevents this.
This DSU erratu
DSU erratum 936184 workaround
If the system is in near idle conditions, this erratum could cause a
deadlock or data corruption. This patch applies the workaround that
prevents this.
This DSU erratum affects only the DSUs that contain the ACP interface
and it was fixed in r2p0. The workaround is applied only to the DSUs
that are actually affected.
Link to respective Arm documentation:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.epm138168/index.html
Change-Id: I033213b3077685130fc1e3f4f79c4d15d7483ec9
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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| #
608529aa |
| 08-Jun-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1397 from dp-arm/dp/cortex-a76
Add support for Cortex-A76 and Cortex-Ares
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| #
040b546e |
| 26-Mar-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Implement Cortex-Ares 1043202 erratum workaround
The workaround uses the instruction patching feature of the Ares cpu.
Change-Id: I868fce0dc0e8e41853dcce311f01ee3867aabb59
Signed-off-by: Dimitris P
Implement Cortex-Ares 1043202 erratum workaround
The workaround uses the instruction patching feature of the Ares cpu.
Change-Id: I868fce0dc0e8e41853dcce311f01ee3867aabb59
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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|