| #
a5394205 |
| 24-Jun-2021 |
bipin.ravi <bipin.ravi@arm.com> |
Merge "errata: workaround for Cortex A78 errata 1821534" into integration
|
| #
1a691455 |
| 30-Apr-2021 |
johpow01 <john.powell@arm.com> |
errata: workaround for Cortex A78 errata 1821534
Cortex A78 erratum 1821534 is a Cat B erratum present in r0p0 and
r1p0 of the A78 processor core, it is fixed in r1p1.
SDEN can be found here:
https
errata: workaround for Cortex A78 errata 1821534
Cortex A78 erratum 1821534 is a Cat B erratum present in r0p0 and
r1p0 of the A78 processor core, it is fixed in r1p1.
SDEN can be found here:
https://documentation-service.arm.com/static/603e3733492bde1625aa8780
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I71057c4b9625cd9edc1a06946b453cf16ae5ea2c
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| #
3f0bec7c |
| 03-May-2021 |
johpow01 <john.powell@arm.com> |
errata: workaround for Cortex A77 errata 1791578
Cortex A77 erratum 1791578 is a Cat B erratum present in r0p0, r1p0,
and r1p1 of the A77 processor core, it is still open.
SDEN can be found here:
h
errata: workaround for Cortex A77 errata 1791578
Cortex A77 erratum 1791578 is a Cat B erratum present in r0p0, r1p0,
and r1p1 of the A77 processor core, it is still open.
SDEN can be found here:
https://documentation-service.arm.com/static/60a63a3c982fc7708ac1c8b1
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ib4b963144f880002de308def12744b982d3df868
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|
| #
de2dd4e7 |
| 07-Apr-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "lib/cpu: Workaround for Cortex A77 erratum 1946167" into integration
|
| #
a492edc4 |
| 23-Mar-2021 |
laurenw-arm <lauren.wehrmeister@arm.com> |
lib/cpu: Workaround for Cortex A77 erratum 1946167
Cortex A77 erratum 1946167 is a Cat B erratum that applies to revisions
<= r1p1. This erratum is avoided by inserting a DMB ST before acquire
atomi
lib/cpu: Workaround for Cortex A77 erratum 1946167
Cortex A77 erratum 1946167 is a Cat B erratum that applies to revisions
<= r1p1. This erratum is avoided by inserting a DMB ST before acquire
atomic instructions without release semantics through a series of
writes to implementation defined system registers.
SDEN can be found here:
https://documentation-service.arm.com/static/600057a29b9c2d1bb22cd1be?token=
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I53e3b4fb7e7575ec83d75c2f132eda5ae0b4f01f
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| #
337e4933 |
| 14-Jan-2021 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes I36e4d672,I47610cee into integration
* changes:
Workaround for Cortex N1 erratum 1946160
Workaround for Cortex A78 erratum 1951500
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| #
263ee781 |
| 07-Oct-2020 |
johpow01 <john.powell@arm.com> |
Workaround for Cortex N1 erratum 1946160
Cortex N1 erratum 1946160 is a Cat B erratum present in r0p0, r1p0,
r2p0, r3p0, r3p1, r4p0, and r4p1. The workaround is to insert a DMB ST
before acquire at
Workaround for Cortex N1 erratum 1946160
Cortex N1 erratum 1946160 is a Cat B erratum present in r0p0, r1p0,
r2p0, r3p0, r3p1, r4p0, and r4p1. The workaround is to insert a DMB ST
before acquire atomic instructions without release semantics. This
issue is present starting from r0p0 but this workaround applies to
revisions r3p0, r3p1, r4p0, and r4p1, for previous revisions there is no
workaround.
SDEN can be found here:
https://documentation-service.arm.com/static/5fa9304cd8dacc30eded464f
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I36e4d6728c275f1c2477dcee9b351077cf7c53e4
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|
| #
3a2710dc |
| 07-Oct-2020 |
johpow01 <john.powell@arm.com> |
Workaround for Cortex A78 erratum 1951500
Cortex A78 erratum 1951500 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to insert a DMB ST before
acquire atomic in
Workaround for Cortex A78 erratum 1951500
Cortex A78 erratum 1951500 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to insert a DMB ST before
acquire atomic instructions without release semantics. This workaround
works on revisions r1p0 and r1p1, in r0p0 there is no workaround.
SDEN can be found here:
https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I47610cee75af6a127ea65edc4d5cffc7e6a2d0a3
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| #
031d479d |
| 12-Jan-2021 |
bipin.ravi <bipin.ravi@arm.com> |
Merge "Workaround for Cortex A78 erratum 1941498" into integration
|
| #
e26c59d2 |
| 06-Oct-2020 |
johpow01 <john.powell@arm.com> |
Workaround for Cortex A78 erratum 1941498
Cortex A78 erratum 1941498 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to set bit 8 in the ECTLR_EL1
register, the
Workaround for Cortex A78 erratum 1941498
Cortex A78 erratum 1941498 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to set bit 8 in the ECTLR_EL1
register, there is a small performance cost (<0.5%) for setting this bit.
SDEN can be found here:
https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I959cee8e3d46c1b84ff5e4409ce5945e459cc6a9
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| #
bc607ccc |
| 18-Dec-2020 |
bipin.ravi <bipin.ravi@arm.com> |
Merge "Workaround for Cortex A76 erratum 1946160" into integration
|
| #
3f0d8369 |
| 16-Dec-2020 |
johpow01 <john.powell@arm.com> |
Workaround for Cortex A76 erratum 1946160
Cortex A76 erratum 1946160 is a Cat B erratum, present in some revisions
of the A76 processor core. The workaround is to insert a DMB ST before
acquire ato
Workaround for Cortex A76 erratum 1946160
Cortex A76 erratum 1946160 is a Cat B erratum, present in some revisions
of the A76 processor core. The workaround is to insert a DMB ST before
acquire atomic instructions without release semantics. This issue is
present in revisions r0p0 - r4p1 but this workaround only applies to
revisions r3p0 - r4p1, there is no workaround for older versions.
SDEN can be found here:
https://documentation-service.arm.com/static/5fbb77d7d77dd807b9a80cc1
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ief33779ee76a89ce2649812ae5214b86a139e327
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| #
9dd2896e |
| 01-Dec-2020 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge "Add support for Neoverse-N2 CPUs." into integration
|
| #
25bbbd2d |
| 23-Oct-2020 |
Javier Almansa Sobrino <javier.almansasobrino@arm.com> |
Add support for Neoverse-N2 CPUs.
Enable basic support for Neoverse-N2 CPUs.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8
Add support for Neoverse-N2 CPUs.
Enable basic support for Neoverse-N2 CPUs.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8ad
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| #
7b12a8d6 |
| 19-Nov-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "Revert workaround for A77 erratum 1800714" into integration
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| #
b9ad2bb8 |
| 19-Nov-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "Revert workaround for A76 erratum 1800710" into integration
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| #
9bbc03a6 |
| 12-Nov-2020 |
johpow01 <john.powell@arm.com> |
Revert workaround for A77 erratum 1800714
This errata workaround did not work as intended and was revised in
subsequent SDEN releases so we are reverting this change.
This is the patch being revert
Revert workaround for A77 erratum 1800714
This errata workaround did not work as intended and was revised in
subsequent SDEN releases so we are reverting this change.
This is the patch being reverted:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4686
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I8554c75d7217331c7effd781b5f7f49b781bbebe
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| #
95ed9a9e |
| 12-Nov-2020 |
johpow01 <john.powell@arm.com> |
Revert workaround for A76 erratum 1800710
This errata workaround did not work as intended and was revised in
subsequent SDEN releases so we are reverting this change.
This is the patch being revert
Revert workaround for A76 erratum 1800710
This errata workaround did not work as intended and was revised in
subsequent SDEN releases so we are reverting this change.
This is the patch being reverted:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4684
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I560749a5b55e22fbe49d3f428a8b9545d6bdaaf0
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| #
7d3a7ec7 |
| 09-Oct-2020 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge "Workaround for Cortex A77 erratum 1925769" into integration
|
| #
35c75377 |
| 10-Sep-2020 |
johpow01 <john.powell@arm.com> |
Workaround for Cortex A77 erratum 1925769
Cortex A77 erratum 1925769 is a Cat B erratum, present in older
revisions of the Cortex A77 processor core. The workaround is to
set bit 8 in the ECTLR_EL1
Workaround for Cortex A77 erratum 1925769
Cortex A77 erratum 1925769 is a Cat B erratum, present in older
revisions of the Cortex A77 processor core. The workaround is to
set bit 8 in the ECTLR_EL1 register, there is a small performance cost
(<0.5%) for setting this bit.
SDEN can be found here:
https://documentation-service.arm.com/static/5f7c35d0d3be967f7be46d33
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I9cf0e0b5dc1e3e32e24279d2632c759cc7bd7ce9
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|
| #
f8dee97b |
| 05-Oct-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "Workaround for Cortex A76 erratum 1868343" into integration
|
| #
55ff05f3 |
| 29-Sep-2020 |
johpow01 <john.powell@arm.com> |
Workaround for Cortex A76 erratum 1868343
Cortex A76 erratum 1868343 is a Cat B erratum, present in older
revisions of the Cortex A76 processor core. The workaround is to
set a bit in the CPUACTLR_
Workaround for Cortex A76 erratum 1868343
Cortex A76 erratum 1868343 is a Cat B erratum, present in older
revisions of the Cortex A76 processor core. The workaround is to
set a bit in the CPUACTLR_EL1 system register, which delays instruction
fetch after branch misprediction. This workaround will have a small
impact on performance.
This workaround is the same as workarounds for errata 1262606 and
1275112, so all 3 have been combined into one function call.
SDEN can be found here:
https://documentation-service.arm.com/static/5f2bed6d60a93e65927bc8e7
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7f2f9965f495540a1f84bb7dcc28aff45d6cee5d
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| #
c36aa3cf |
| 29-Sep-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "Workaround for Cortex A77 erratum 1508412" into integration
|
| #
aa3efe3d |
| 14-Jul-2020 |
laurenw-arm <lauren.wehrmeister@arm.com> |
Workaround for Cortex A77 erratum 1508412
Cortex A77 erratum 1508412 is a Cat B Errata present in r0p0 and r1p0.
The workaround is a write sequence to several implementation defined
registers based
Workaround for Cortex A77 erratum 1508412
Cortex A77 erratum 1508412 is a Cat B Errata present in r0p0 and r1p0.
The workaround is a write sequence to several implementation defined
registers based on A77 revision.
This errata is explained in this SDEN:
https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I217993cffb3ac57c313db8490e7b8a7bb393379b
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| #
238db174 |
| 11-Sep-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "Workaround for Neoverse N1 erratum 1868343" into integration
|