| #
7d1700c4 |
| 11-Jan-2023 |
Sona Mathew <SonaRebecca.Mathew@arm.com> |
fix(cpus): workaround for Cortex-A78 erratum 2779479
Cortex-A78 erratum 2779479 is a Cat B erratum that applies to all revisions <= r1p2 and is still open.
The workaround is to set the CPUACTLR3_EL
fix(cpus): workaround for Cortex-A78 erratum 2779479
Cortex-A78 erratum 2779479 is a Cat B erratum that applies to all revisions <= r1p2 and is still open.
The workaround is to set the CPUACTLR3_EL1[47] bit to 1. Setting this bit might have a small impact on power and negligible impact on performance.
SDEN documentation: https://developer.arm.com/documentation/SDEN1401784/latest
Change-Id: I3779fd1eff3017c5961ffa101b357918070b3b36 Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
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| #
00230e37 |
| 18-Jan-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Cortex-A78C erratum 2772121
Cortex-A78C erratum 2772121 is a Cat B erratum that applies to all revisions <=r0p2 and is still open. The workaround is to insert a dsb before
fix(cpus): workaround for Cortex-A78C erratum 2772121
Cortex-A78C erratum 2772121 is a Cat B erratum that applies to all revisions <=r0p2 and is still open. The workaround is to insert a dsb before the isb in the power down sequence.
SDEN documentation: https://developer.arm.com/documentation/SDEN1707916/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I0e190dabffc20c4d3b9b98d1abeb50f308b80bb9
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| #
72020318 |
| 11-Jan-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(cpus): workaround for Cortex-X2 erratum 2282622" into integration
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| #
fb797974 |
| 11-Jan-2023 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge "fix(cpus): workaround for Cortex-A710 erratum 2282622" into integration
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| #
f9c6301d |
| 22-Dec-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Cortex-X2 erratum 2282622
Cortex-X2 erratum 2282622 is a Cat B erratum that applies to all revisions <=r2p1 and is still open. The workaround is to set CPUACTLR2_EL1[0] to
fix(cpus): workaround for Cortex-X2 erratum 2282622
Cortex-X2 erratum 2282622 is a Cat B erratum that applies to all revisions <=r2p1 and is still open. The workaround is to set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidations to other PE caches.
SDEN documentation: https://developer.arm.com/documentation/SDEN1775100/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I43956aa4898a8608eedc5d0dd1471172c641a0c6
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| #
89d85ad0 |
| 22-Dec-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Cortex-A710 erratum 2282622
Cortex-A710 erratum 2282622 is a Cat B erratum that applies to all revisions <=r2p1 and is still open. The workaround was earlier applied to all
fix(cpus): workaround for Cortex-A710 erratum 2282622
Cortex-A710 erratum 2282622 is a Cat B erratum that applies to all revisions <=r2p1 and is still open. The workaround was earlier applied to all revisions <= r2p0, this patch extends it to r2p1. This was thought to have been fixed in r2p1 which is not the case.
SDEN documentation: https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: Iad38a7fe57bec3f2d8977995acd601dcd9ae69c0
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| #
c3c30ff8 |
| 21-Dec-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(cpus): workaround for Neoverse N2 erratum 2743089" into integration
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| #
1ee7c823 |
| 07-Dec-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Neoverse N2 erratum 2743089
Neoverse N2 erratum 2743089 is a Cat B erratum that applies to all revisions <=r0p2 and is fixed in r0p3. The workaround is to insert a dsb befo
fix(cpus): workaround for Neoverse N2 erratum 2743089
Neoverse N2 erratum 2743089 is a Cat B erratum that applies to all revisions <=r0p2 and is fixed in r0p3. The workaround is to insert a dsb before the isb in the power down sequence.
SDEN documentation: https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: Idec862226bd32c91374a8bbd5d73d7ee480a34d9
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| #
e7abef90 |
| 21-Dec-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I0362da46,I8ee7c16c into integration
* changes: fix(cpus): workaround for Cortex-A78 erratum 2772019 fix(cpus): workaround for Neoverse V1 erratum 2743093
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| #
b10afcce |
| 15-Dec-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Cortex-A78 erratum 2772019
Cortex-A78 erratum 2772019 is a Cat B erratum that applies to all revisions <=r1p2 and is still open. The workaround is to insert a dsb before th
fix(cpus): workaround for Cortex-A78 erratum 2772019
Cortex-A78 erratum 2772019 is a Cat B erratum that applies to all revisions <=r1p2 and is still open. The workaround is to insert a dsb before the isb in the power down sequence.
SDEN documentation: https://developer.arm.com/documentation/SDEN1401784/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I0362da463eca777aa7a385bcdeb39b8549799f02
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| #
31747f05 |
| 15-Dec-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Neoverse V1 erratum 2743093
Neoverse V1 erratum 2743093 is a Cat B erratum that applies to all revisions <=r1p2 and is still open. The workaround is to insert a dsb before
fix(cpus): workaround for Neoverse V1 erratum 2743093
Neoverse V1 erratum 2743093 is a Cat B erratum that applies to all revisions <=r1p2 and is still open. The workaround is to insert a dsb before the isb in the power down sequence.
SDEN documentation: https://developer.arm.com/documentation/SDEN1401781/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I8ee7c16c14c4fd6ee35d20c855273ecfce0d1b32
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| #
19e09e27 |
| 14-Dec-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes Ib02688f7,If17fe04d into integration
* changes: fix(cpus): workaround for Cortex-X2 erratum 2768515 fix(cpus): workaround for Cortex-A710 erratum 2768515
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| #
1cfde822 |
| 07-Dec-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Cortex-X2 erratum 2768515
Cortex-X2 erratum 2768515 is a Cat B erratum that applies to all revisions <=r2p1 and is still open. The workaround is to insert a dsb before the
fix(cpus): workaround for Cortex-X2 erratum 2768515
Cortex-X2 erratum 2768515 is a Cat B erratum that applies to all revisions <=r2p1 and is still open. The workaround is to insert a dsb before the isb in the power down sequence.
SDEN documentation: https://developer.arm.com/documentation/SDEN1775100/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: Ib02688f7b6dc7f6ec305e68e8895174f6fd577a0
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| #
b87b02cf |
| 07-Dec-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Cortex-A710 erratum 2768515
Cortex-A710 erratum 2768515 is a Cat B erratum that applies to all revisions <=r2p1 and is still open. The workaround is to insert a dsb before
fix(cpus): workaround for Cortex-A710 erratum 2768515
Cortex-A710 erratum 2768515 is a Cat B erratum that applies to all revisions <=r2p1 and is still open. The workaround is to insert a dsb before the isb in the power down sequence.
SDEN documentation: https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: If17fe04d3fda0dba6b8aabdd837a1c53e1830ed5
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| #
d3d2a5a4 |
| 28-Nov-2022 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge "fix(cpus): workaround for Cortex-X3 erratum 2615812" into integration
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| #
c7e698cf |
| 11-Nov-2022 |
Harrison Mutai <harrison.mutai@arm.com> |
fix(cpus): workaround for Cortex-X3 erratum 2615812
Cortex-X3 erratum 2615812 is a Cat B erratum that applies to revisions r0p0, r1p0, and r1p1, and is still open. The workaround is to disable the u
fix(cpus): workaround for Cortex-X3 erratum 2615812
Cortex-X3 erratum 2615812 is a Cat B erratum that applies to revisions r0p0, r1p0, and r1p1, and is still open. The workaround is to disable the use of the Full Retention power mode in the core (setting WFI_RET_CTRL and WFE_RET_CTRL in CORTEX_X3_IMP_CPUPWRCTLR_EL1 to 0b000).
SDEN can be found here: https://developer.arm.com/documentation/SDEN2055130/latest
Change-Id: I5ad66df3e18fc85a6b23f6662239494ee001d82f Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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| #
2b138c6b |
| 11-Nov-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "fix(cpus): workaround for Cortex-A77 erratum 2743100" into integration
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| #
4fdeaffe |
| 01-Nov-2022 |
Boyan Karatotev <boyan.karatotev@arm.com> |
fix(cpus): workaround for Cortex-A77 erratum 2743100
Cortex-A77 erratum 2743100 is a Cat B erratum that applies to revisions r0p0, r1p0, r1p1, and is still open. The workaround is to insert a dsb be
fix(cpus): workaround for Cortex-A77 erratum 2743100
Cortex-A77 erratum 2743100 is a Cat B erratum that applies to revisions r0p0, r1p0, r1p1, and is still open. The workaround is to insert a dsb before the isb in the power down sequence.
SDEN can be found here: https://developer.arm.com/documentation/SDEN1152370/latest
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I8e49a2dac8611f31ace249a17ae7a90cd60e742a
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| #
c87e1f62 |
| 09-Nov-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "errata" into integration
* changes: fix(cpus): workaround for Cortex-A76 erratum 2743102 fix(cpus): workaround for Neoverse N1 erratum 2743102
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| #
49273098 |
| 02-Nov-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Cortex-A76 erratum 2743102
Cortex-A76 erratum 2743102 is a Cat B erratum that applies to all revisions <=r4p1 and is still open. The workaround is to insert a dsb before th
fix(cpus): workaround for Cortex-A76 erratum 2743102
Cortex-A76 erratum 2743102 is a Cat B erratum that applies to all revisions <=r4p1 and is still open. The workaround is to insert a dsb before the isb in the power down sequence.
SDEN documentation: https://developer.arm.com/documentation/SDEN885749/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: Ie2cd73bd91417d30b5633d80b2fbee32944bc2de
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| #
8ce40503 |
| 02-Nov-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Neoverse N1 erratum 2743102
Neoverse N1 erratum 2743102 is a Cat B erratum that applies to all revisions <=r4p1 and is still open. The workaround is to insert a dsb before
fix(cpus): workaround for Neoverse N1 erratum 2743102
Neoverse N1 erratum 2743102 is a Cat B erratum that applies to all revisions <=r4p1 and is still open. The workaround is to insert a dsb before the isb in the power down sequence.
SDEN documentation: https://developer.arm.com/documentation/SDEN885747/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I81a8793c1a118764df3ac97b67f5e088f56f6a20
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| #
92b62c16 |
| 27-Oct-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge changes I7d3a97df,I5935b4bc,I9a325c5b,Ie29bd3a5,Iebb90cf2 into integration
* changes: fix(cpus): workaround for Cortex-A710 erratum 2291219 fix(cpus): workaround for Cortex-X3 erratum 2313
Merge changes I7d3a97df,I5935b4bc,I9a325c5b,Ie29bd3a5,Iebb90cf2 into integration
* changes: fix(cpus): workaround for Cortex-A710 erratum 2291219 fix(cpus): workaround for Cortex-X3 erratum 2313909 fix(cpus): workaround for Neoverse-N2 erratum 2326639 fix(rpi3): tighten platform pwr_domain_pwr_down_wfi behaviour chore: rename Makalu ELP to Cortex-X3
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| #
888eafa0 |
| 03-Oct-2022 |
Boyan Karatotev <boyan.karatotev@arm.com> |
fix(cpus): workaround for Cortex-A710 erratum 2291219
Cortex-A710 erratum 2291219 is a Cat B erratum that applies to revisions r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set CP
fix(cpus): workaround for Cortex-A710 erratum 2291219
Cortex-A710 erratum 2291219 is a Cat B erratum that applies to revisions r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set CPUACTLR2_EL1[36] to 1 before the power down sequence that sets CORE_PWRDN_EN. This allows the cpu to retry the power down and prevents the deadlock. TF-A never clears this bit even if it wakes up from the wfi in the sequence since it is not expected to do anything but retry to power down after and the bit is cleared on reset.
SDEN can be found here: https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I7d3a97dfac0c433c0be386c1f3d2f2e895a3f691
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| #
79544126 |
| 03-Oct-2022 |
Boyan Karatotev <boyan.karatotev@arm.com> |
fix(cpus): workaround for Cortex-X3 erratum 2313909
Cortex-X3 erratum 2313909 is a Cat B erratum that applies to revisions r0p0 and r1p0, and is fixed in r1p1. The workaround is to set CPUACTLR2_EL1
fix(cpus): workaround for Cortex-X3 erratum 2313909
Cortex-X3 erratum 2313909 is a Cat B erratum that applies to revisions r0p0 and r1p0, and is fixed in r1p1. The workaround is to set CPUACTLR2_EL1[36] to 1 before the power down sequence that sets CORE_PWRDN_EN. This allows the cpu to retry the power down and prevents the deadlock. TF-A never clears this bit even if it wakes up from the wfi in the sequence since it is not expected to do anything but retry to power down after and the bit is cleared on reset.
SDEN can be found here: https://developer.arm.com/documentation/SDEN2055130/latest
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I5935b4bcd1e6712477c0d6eab2acc96d7964a35d
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| #
43438ad1 |
| 03-Oct-2022 |
Boyan Karatotev <boyan.karatotev@arm.com> |
fix(cpus): workaround for Neoverse-N2 erratum 2326639
Neoverse-N2 erratum 2326639 is a Cat B erratum that applies to revision r0p0 and is fixed in r0p1. The workaround is to set CPUACTLR2_EL1[36] to
fix(cpus): workaround for Neoverse-N2 erratum 2326639
Neoverse-N2 erratum 2326639 is a Cat B erratum that applies to revision r0p0 and is fixed in r0p1. The workaround is to set CPUACTLR2_EL1[36] to 1 before the power down sequence that sets CORE_PWRDN_EN. This allows the cpu to retry the power down and prevents the deadlock. TF-A never clears this bit even if it wakes up from the wfi in the sequence since it is not expected to do anything but retry to power down after and the bit is cleared on reset.
SDEN can be found here: https://developer.arm.com/documentation/SDEN1982442/latest/
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I9a325c5b9b498798e5efd5c79a4a6d5bed97c619
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|