fix(cpus): workaround for C1-Premium erratum 3651221

C1-Premium erratum 3651221 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

The erratum can be avoided by disabling th

fix(cpus): workaround for C1-Premium erratum 3651221

C1-Premium erratum 3651221 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

The erratum can be avoided by disabling the affected prefetcher
setting CPUACTLR6_EL1[41] to 1.

SDEN documentation:
https://developer.arm.com/documentation/111078/latest

Change-Id: I5ebe282be8f88fb2fcc1d33cec9c1db144316077
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for C1-Premium erratum 3502731

C1-Premium erratum 3502731 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

The erratum can be avoided by setting CPUA

fix(cpus): workaround for C1-Premium erratum 3502731

C1-Premium erratum 3502731 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

The erratum can be avoided by setting CPUACTLR4[23] to 1,
which will disable Memory Renaming optimization.
The performance impact of setting this chicken bit is about
0.82% in GB6.

SDEN documentation:
https://developer.arm.com/documentation/111078/latest

Change-Id: Idc6ec2a742ed0f974d026aa63d7c9c5b248ef33b
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-A720AE erratum 3456103

Cortex-A720AE erratum 3456103 is a Cat B erratum that applies
to revisions r0p0 and r0p1, and is still open.

This errata can be avoided by ad

fix(cpus): workaround for Cortex-A720AE erratum 3456103

Cortex-A720AE erratum 3456103 is a Cat B erratum that applies
to revisions r0p0 and r0p1, and is still open.

This errata can be avoided by adding a speculation barrier
instruction following writes to the SSBS register to
ensure the new value of PSTATE.SSBS affects the subsequent
instructions in the execution stream under speculation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3090091

Change-Id: Ia240a697d8e99bd4fbf4c92720d5228513080088
Signed-off-by: John Powell <john.powell@arm.com>

show more ...

fix(cpus): workaround for Cortex-A720 erratum 3456091

Cortex-A720 erratum 3456091 is a Cat B erratum that applies
to revisions r0p0, r0p1 and r0p2, and is still open.

This errata can be avoided by

fix(cpus): workaround for Cortex-A720 erratum 3456091

Cortex-A720 erratum 3456091 is a Cat B erratum that applies
to revisions r0p0, r0p1 and r0p2, and is still open.

This errata can be avoided by adding a speculation barrier
instruction following writes to the SSBS register to
ensure the new value of PSTATE.SSBS affects the subsequent
instructions in the execution stream under speculation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2439421

Change-Id: Ia22a0d6bb98d1a0edb11d2469beab22c7f7aba3a
Signed-off-by: John Powell <john.powell@arm.com>

show more ...

fix(cpus): workaround for Cortex-A715 erratum 3456084

Cortex-A715 erratum 3456084 is a Cat B erratum that applies
to revisions r0p0, r1p0, r1p1, r1p2 and r1p3, and is still open.

This errata can be

fix(cpus): workaround for Cortex-A715 erratum 3456084

Cortex-A715 erratum 3456084 is a Cat B erratum that applies
to revisions r0p0, r1p0, r1p1, r1p2 and r1p3, and is still open.

This errata can be avoided by adding a speculation barrier
instruction following writes to the SSBS register to
ensure the new value of PSTATE.SSBS affects the subsequent
instructions in the execution stream under speculation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2148827

Change-Id: Ie3f2b46051539cdebc151c46f80045a7156e0386
Signed-off-by: John Powell <john.powell@arm.com>

show more ...

fix(cpus): workaround for Cortex-X2 erratum 3324338

Cortex-X2 erratum 3324338 is a Cat B erratum that applies
to revisions r0p0, r1p0, r2p0 and r2p1, and is still open.

This errata can be avoided b

fix(cpus): workaround for Cortex-X2 erratum 3324338

Cortex-X2 erratum 3324338 is a Cat B erratum that applies
to revisions r0p0, r1p0, r2p0 and r2p1, and is still open.

This errata can be avoided by adding a speculation barrier
instruction following writes to the SSBS register to
ensure the new value of PSTATE.SSBS affects the subsequent
instructions in the execution stream under speculation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100

Change-Id: Ibbe55a55bd6cf5e159dab92a78ecb55c5a4d7eb1
Signed-off-by: John Powell <john.powell@arm.com>

show more ...

fix(cpus): workaround for Cortex-A710 erratum 3324338

Cortex-A710 erratum 3324338 is a Cat B erratum that applies
to revisions r0p0, r1p0, r2p0 and r2p1, and is still open.

This errata can be avoid

fix(cpus): workaround for Cortex-A710 erratum 3324338

Cortex-A710 erratum 3324338 is a Cat B erratum that applies
to revisions r0p0, r1p0, r2p0 and r2p1, and is still open.

This errata can be avoided by adding a speculation barrier
instruction following writes to the SSBS register to
ensure the new value of PSTATE.SSBS affects the subsequent
instructions in the execution stream under speculation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101

Change-Id: I9325f3715f4fa17bfb7ded9d5c69c59645f65b27
Signed-off-by: John Powell <john.powell@arm.com>

show more ...

Merge changes from topic "xl/c1ultra-errata" into integration

* changes:
fix(cpus): workaround for C1-Ultra erratum 3324333
fix(cpus): workaround for C1-Ultra erratum 3658374
fix(cpus): workar

Merge changes from topic "xl/c1ultra-errata" into integration

* changes:
fix(cpus): workaround for C1-Ultra erratum 3324333
fix(cpus): workaround for C1-Ultra erratum 3658374
fix(cpus): workaround for C1-Ultra erratum 3926381
fix(cpus): workaround for C1-Ultra erratum 4102704
fix(cpus): workaround for C1-Ultra erratum 3865171
fix(cpus): workaround for C1-Ultra erratum 3815514
fix(cpus): workaround for C1-Ultra erratum 3705939
fix(cpus): workaround for C1-Ultra erratum 3684152
fix(cpus): workaround for C1-Ultra erratum 3651221
fix(cpus): workaround for C1-Ultra erratum 3502731

show more ...

fix(cpus): workaround for C1-Ultra erratum 3324333

C1-Ultra erratum 3324333 is a Cat B erratum that applies
to revision r0p0, and is fixed in r1p0.

This errata can be avoid by having a speculation

fix(cpus): workaround for C1-Ultra erratum 3324333

C1-Ultra erratum 3324333 is a Cat B erratum that applies
to revision r0p0, and is fixed in r1p0.

This errata can be avoid by having a speculation barrier
instruction following writes to the SSBS register to
ensure the new value of PSTATE.SSBS affects the subsequent
instructions in the execution stream under speculation.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I203238cbb8561cee683c22a6dbe4742702f82763
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for C1-Ultra erratum 3658374

C1-Ultra erratum 3658374 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

This is workaround for accessing ICH_VMCR_EL2.

fix(cpus): workaround for C1-Ultra erratum 3658374

C1-Ultra erratum 3658374 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

This is workaround for accessing ICH_VMCR_EL2.
When ICH_VMCR_EL2.VBPR1 is written in Secure state (SCR_EL3.NS==0)
and then subsequently read in Non-secure state (SCR_EL3.NS==1), a
wrong value might be returned. The same issue exists in the opposite way.

Adding workaround in EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored. For example, EL3 software should set
SCR_EL3.NS to 1 when saving or restoring the value ICH_VMCR_EL2 for
Non-secure(or Realm) state. EL3 software should clear
SCR_EL3.NS to 0 when saving or restoring the value ICH_VMCR_EL2 for
Secure state.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I945477b2432fefc04049e8576b66cea0cbffb03a
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for C1-Ultra erratum 3926381

C1-Ultra erratum 3926381 is a Cat B erratum that applies
to revision r1p0 and is open.

This errata can be avoided by executing an implementation
s

fix(cpus): workaround for C1-Ultra erratum 3926381

C1-Ultra erratum 3926381 is a Cat B erratum that applies
to revision r1p0 and is open.

This errata can be avoided by executing an implementation
specific instruction patching sequence as soon as possible
after boot. After it is applied, the code only converts
WFx and WFxT instructions to NOP when PSTATE.SM=1 or when
PSTATE.ZA=1.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I2e0f3a715670aaac116c7d3c5f5992ff7ab05ba3
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for C1-Ultra erratum 4102704

C1-Ultra erratum 4102704 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR

fix(cpus): workaround for C1-Ultra erratum 4102704

C1-Ultra erratum 4102704 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR4_EL1[23] to 1.
Overall expected performance degradation is ~1.36%, but
isolated benchmark components might see higher or lower impact.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I414df1af006484dd120f928bd8fdf9e6f4a513fd
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for C1-Ultra erratum 3865171

C1-Ultra erratum 3865171 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR

fix(cpus): workaround for C1-Ultra erratum 3865171

C1-Ultra erratum 3865171 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR2_EL1[22] to 1,
which will disable linking multiple Non-Cacheable or Device
GRE loads to the same read request for the cache-line. This
might have a significant performance impact to Non-cacheable
and Device GRE read bandwidth for streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I8bfe15fdd1d028d43d8730e7d43f72c9f15810d7
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for C1-Ultra erratum 3815514

C1-Ultra erratum 3815514 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR

fix(cpus): workaround for C1-Ultra erratum 3815514

C1-Ultra erratum 3815514 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR5_EL1[13] to 1.
Setting CPUACTLR5_EL1[13] to 1 is expected to result in a small
performance degradation for workloads that use MTE. The
degradation might be approximately 1.6% when using MTE imprecise
mode or 0.9% for MTE precise mode.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I2d6b0ee282010139d8dc406800f2738b39113957
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for C1-Ultra erratum 3705939

C1-Ultra erratum 3705939 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR

fix(cpus): workaround for C1-Ultra erratum 3705939

C1-Ultra erratum 3705939 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR_EL1[48] to 1,
which disables a RDFFR optimization. Setting this bit has
negligible impact on GB6/SPECint performance, but will have an
impact on SVE RDFFR performance.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I88343236af86a9bb0b0ce644296d5929d7b956d1
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for C1-Ultra erratum 3684152

C1-Ultra erratum 3684152 is a Cat B erratum that applies
to revision r0p0, and is fixed in r1p0.

The erratum can be avoided by setting CPUACTLR_EL

fix(cpus): workaround for C1-Ultra erratum 3684152

C1-Ultra erratum 3684152 is a Cat B erratum that applies
to revision r0p0, and is fixed in r1p0.

The erratum can be avoided by setting CPUACTLR_EL1[60:58] to
3'b001, which has a small perf impact.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I3747b2a99785602bd2a3bddac3a69a934e7f4b37
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for C1-Ultra erratum 3651221

C1-Ultra erratum 3651221 is a Cat B erratum that applies
to revision r0p0, and is fixed in r1p0.

The erratum can be avoided by disabling the affec

fix(cpus): workaround for C1-Ultra erratum 3651221

C1-Ultra erratum 3651221 is a Cat B erratum that applies
to revision r0p0, and is fixed in r1p0.

The erratum can be avoided by disabling the affected prefetcher
by setting CPUACTLR6_EL1[41] to 1.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: I0498a81a62bbea666b503cdd5a6dbcae7eab0dce
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for C1-Ultra erratum 3502731

C1-Ultra erratum 3502731 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

The erratum can be avoided by setting CPUACTLR

fix(cpus): workaround for C1-Ultra erratum 3502731

C1-Ultra erratum 3502731 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

The erratum can be avoided by setting CPUACTLR4[23] to 1,
which will disable Memory Renaming optimization.
The performance impact of setting this chicken bit is about
0.82% in GB6.

SDEN documentation:
https://developer.arm.com/documentation/111077/8-0

Change-Id: Iaf832b66aeed937edbb1e9be29de41b0f2b5d70c
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

Merge changes from topic "xl/a725-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A725 erratum 3456106
fix(cpus): workaround for Cortex-A725 erratum 3711914
fix(cpus): wor

Merge changes from topic "xl/a725-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A725 erratum 3456106
fix(cpus): workaround for Cortex-A725 erratum 3711914
fix(cpus): workaround for Cortex-A725 erratum 2936490
fix(cpus): workaround for Cortex-A725 erratum 2874943

show more ...

Merge changes from topic "xl/a65-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A65 erratum 1541130
fix(cpus): workaround for Cortex-A65 erratum 1227419
fix(cpus): workar

Merge changes from topic "xl/a65-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A65 erratum 1541130
fix(cpus): workaround for Cortex-A65 erratum 1227419
fix(cpus): workaround for Cortex-A65 erratum 1179935

show more ...

Merge changes from topic "xl/a76ae-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A76AE erratum 2371140
fix(cpus): workaround for Cortex-A76AE erratum 1969401
fix(cpus):

Merge changes from topic "xl/a76ae-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A76AE erratum 2371140
fix(cpus): workaround for Cortex-A76AE erratum 1969401
fix(cpus): workaround for Cortex-A76AE erratum 1931435
fix(cpus): workaround for Cortex-A76AE erratum 1931427

show more ...

fix(cpus): workaround for Cortex-A725 erratum 3456106

Cortex-A725 erratum 3456106 is a Cat B erratum that applies
to revisions r0p0, r0p1 and r0p2, it is still open.

This erratum can be avoided by

fix(cpus): workaround for Cortex-A725 erratum 3456106

Cortex-A725 erratum 3456106 is a Cat B erratum that applies
to revisions r0p0, r0p1 and r0p2, it is still open.

This erratum can be avoided by having Speculation Barrier (SB)
instruction after the writes to the PSTATE.SSBS.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2832921/latest/

Change-Id: I10d1e8cb4da19ba4101a5617245ff75866707d25
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-A65 erratum 1541130

Cortex-A65 erratum 1541130 is a Cat B erratum that applies
to r0p0, r1p0, r1p1, r1p2 revisions of the CPU and is still open.

This erratum can be

fix(cpus): workaround for Cortex-A65 erratum 1541130

Cortex-A65 erratum 1541130 is a Cat B erratum that applies
to r0p0, r1p0, r1p1, r1p2 revisions of the CPU and is still open.

This erratum can be avoided by disable stage1 page table walk for
lower Els (EL1 and EL0) in EL3, so 'AT' speculative fetch at any
point produces either the correct result or failure without TLB
allocation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1065159/latest/

Change-Id: I72498f60f8449193ed4b5b2a9e7a08530e786ec3
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-A725 erratum 3711914

Cortex-A725 erratum 3711914 is a Cat B erratum that applies
to revisions r0p0 and r0p1 and it is fixed in r0p2.

This erratum can be avoided by

fix(cpus): workaround for Cortex-A725 erratum 3711914

Cortex-A725 erratum 3711914 is a Cat B erratum that applies
to revisions r0p0 and r0p1 and it is fixed in r0p2.

This erratum can be avoided by inserting a DMB LD after each DSB ST instruction.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2832921/latest/

Change-Id: If3b9d3a0f495b3a172d3e6e5ca7afa8c30aeb4ea
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-A725 erratum 2936490

Cortex-A725 erratum 2936490 is a Cat B erratum that applies
to revisions in r0p0, and is fixed in r0p1.

This erratum can be avoided by setting

fix(cpus): workaround for Cortex-A725 erratum 2936490

Cortex-A725 erratum 2936490 is a Cat B erratum that applies
to revisions in r0p0, and is fixed in r0p1.

This erratum can be avoided by setting CPUACTLR2_EL1[37] to 1.
Setting this bit is expected to have a negligible performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2832921/latest/

Change-Id: I9833f8831ba3735a94763791a65be11b95c00bdb
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...