| e249e569 | 21-Feb-2024 |
Tamas Ban <tamas.ban@arm.com> |
refactor(rse): change all occurrences of RSS to RSE
Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id
refactor(rse): change all occurrences of RSS to RSE
Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I9f72ad36ec233d7eaac3ce9e2f2b010130e1fa94
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| 3857898f | 21-Feb-2024 |
Tamas Ban <tamas.ban@arm.com> |
refactor(psa): rename all 'rss' files to 'rse'
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I379c471c541dda25d8ee9087fcf67e05b4204474 |
| 024c4948 | 21-Feb-2024 |
Tamas Ban <tamas.ban@arm.com> |
refactor(measured-boot): rename all 'rss' files to 'rse'
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I3bd987456ad0f5c7a003960dd543efad2ce668a8 |
| 95511698 | 21-Feb-2024 |
Tamas Ban <tamas.ban@arm.com> |
refactor(rss): rename all 'rss' files to 'rse'
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I6cfca1d67e246d5079f683241021ed039cc27f74 |
| d6c76e6c | 17-Apr-2024 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
fix(cm): add more feature registers to EL1 context mgmt
The following system registers are made part of save and restore
operations for EL1 context:
TRFCR_EL1
SCXTNUM_EL0
SCXTNUM_EL1
GCSCR_EL1
GCSC
fix(cm): add more feature registers to EL1 context mgmt
The following system registers are made part of save and restore
operations for EL1 context:
TRFCR_EL1
SCXTNUM_EL0
SCXTNUM_EL1
GCSCR_EL1
GCSCRE0_EL1
GCSPR_EL1
GCSPR_EL0
Change-Id: I1077112bdc29a6c9cd39b9707d6cf10b95fa15e3
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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| 832e4ed5 | 19-Apr-2024 |
Soby Mathew <soby.mathew@arm.com> |
fix(gpt): declare gpt_tlbi_by_pa_ll()
The patch 8754cc5 accidentally removes the declaration of
gpt_tlbi_by_pa_ll() and hence breaks RME builds. This patch
fixes the same.
signed-off-by: Soby Mathe
fix(gpt): declare gpt_tlbi_by_pa_ll()
The patch 8754cc5 accidentally removes the declaration of
gpt_tlbi_by_pa_ll() and hence breaks RME builds. This patch
fixes the same.
signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: I2523982fc48bca2a1f1a36fd9bd3803b01c6916a
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| 98f7b60e | 19-Apr-2024 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes Ic40e1b7a,I0398b550,Ife594ed6,I3eb0f29b into integration
* changes:
fix(gpt): unify logging messages
chore(gpt): remove gpt_ prefix
feat(aarch64): add functions for TLBI RPALOS
Merge changes Ic40e1b7a,I0398b550,Ife594ed6,I3eb0f29b into integration
* changes:
fix(gpt): unify logging messages
chore(gpt): remove gpt_ prefix
feat(aarch64): add functions for TLBI RPALOS
feat(locks): add bitlock
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| 8754cc5d | 13-Mar-2024 |
AlexeiFedorov <Alexei.Fedorov@arm.com> |
feat(aarch64): add functions for TLBI RPALOS
This patch adds tlbirpalos_XYZ() functions to support
TLBI RPALOS instructions for the 4KB-512MB invalidation
range.
Change-Id: Ife594ed6c746d356b4b1fdf
feat(aarch64): add functions for TLBI RPALOS
This patch adds tlbirpalos_XYZ() functions to support
TLBI RPALOS instructions for the 4KB-512MB invalidation
range.
Change-Id: Ife594ed6c746d356b4b1fdf97001a0fe2b5e8cd0
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
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| e9398e46 | 16-Apr-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(gicv2): fix SGIR_NSATT bitshift" into integration |
| d3604b35 | 16-Apr-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "lto-fixes" into integration
* changes:
fix(bl1): add missing `__RW_{START,END}__` symbols
fix(fvp): don't check MPIDRs with the power controller in BL1
fix(arm): only
Merge changes from topic "lto-fixes" into integration
* changes:
fix(bl1): add missing `__RW_{START,END}__` symbols
fix(fvp): don't check MPIDRs with the power controller in BL1
fix(arm): only expose `arm_bl2_dyn_cfg_init` to BL2
fix(cm): hide `cm_init_context_by_index` from BL1
fix(bl1): add missing spinlock dependency
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| 222f885d | 13-Mar-2024 |
AlexeiFedorov <Alexei.Fedorov@arm.com> |
feat(locks): add bitlock
This patch adds 'bitlock_t' type and bit_lock() and
bit_unlock() to support locking/release functionality
based on individual bit position. These functions use
atomic bit se
feat(locks): add bitlock
This patch adds 'bitlock_t' type and bit_lock() and
bit_unlock() to support locking/release functionality
based on individual bit position. These functions use
atomic bit set and clear instructions which require
FEAT_LSE mandatory from Armv8.1.
Change-Id: I3eb0f29bbccefe6c0f69061aa701187a6364df0c
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
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| eef240cf | 12-Apr-2024 |
Jacob Kroon <jacob.kroon@gmail.com> |
fix(gicv2): fix SGIR_NSATT bitshift
See https://documentation-service.arm.com/static/5f8ff196f86e16515cdbf969?token=
Fixes: dcb31ff79096fc88b45df8068e5de83b93f833ed
Signed-off-by: Jacob Kroon <jac
fix(gicv2): fix SGIR_NSATT bitshift
See https://documentation-service.arm.com/static/5f8ff196f86e16515cdbf969?token=
Fixes: dcb31ff79096fc88b45df8068e5de83b93f833ed
Signed-off-by: Jacob Kroon <jacob.kroon@gmail.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I79ef17c4538cc3e2d65fedd4dfc2eacf55167bf6
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| 0cf4fda9 | 12-Apr-2024 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(handoff): correct representation of tag_id" into integration |
| a796d5aa | 11-Apr-2024 |
Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
fix(cm): remove ENABLE_FEAT_MTE usage
commit@c282384dbb45b6185b4aba14efebbad110d18e49
removed ENABLE_FEAT_MTE but missed its usage in
context structure declaration path.
All mte regs that are curre
fix(cm): remove ENABLE_FEAT_MTE usage
commit@c282384dbb45b6185b4aba14efebbad110d18e49
removed ENABLE_FEAT_MTE but missed its usage in
context structure declaration path.
All mte regs that are currently context saved/restored
are needed only when FEAT_MTE2 is enabled, so move to
usage of FEAT_MTE2 and remove FEAT_MTE usage
Change-Id: I6b4417485fa6b7f52a31045562600945e48e81b7
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
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|
| 3b48ca17 | 06-Feb-2024 |
Chris Kay <chris.kay@arm.com> |
fix(arm): only expose `arm_bl2_dyn_cfg_init` to BL2
The `arm_bl2_dyn_cfg_init` function is intended exclusively for BL2 - it
should not be compiled for any other bootloader image. This change hides
fix(arm): only expose `arm_bl2_dyn_cfg_init` to BL2
The `arm_bl2_dyn_cfg_init` function is intended exclusively for BL2 - it
should not be compiled for any other bootloader image. This change hides
it for all but BL2.
Change-Id: I9fa95094dcc30f9fa4cc7bc5b3119ceae82df1ea
Signed-off-by: Chris Kay <chris.kay@arm.com>
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| a6b3643c | 06-Feb-2024 |
Chris Kay <chris.kay@arm.com> |
fix(cm): hide `cm_init_context_by_index` from BL1
BL1 requires the context management library but does not use or
implement `cm_init_context_by_index`. This change ensures that is not
compiled into
fix(cm): hide `cm_init_context_by_index` from BL1
BL1 requires the context management library but does not use or
implement `cm_init_context_by_index`. This change ensures that is not
compiled into BL1, as linking with LTO enabled causes an undefined
reference for this function.
Change-Id: I4a4602843bd75bc4f47b3e0c4c5a6efce1514ef6
Signed-off-by: Chris Kay <chris.kay@arm.com>
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| 4b50d758 | 08-Apr-2024 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(cm): add more system registers to EL1 context mgmt" into integration |
| f7c091ea | 03-Apr-2024 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "refactor(arm): remove unused SP_MIN UART macros" into integration |
| ed9bb824 | 25-Mar-2024 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
fix(cm): add more system registers to EL1 context mgmt
The following system registers are made part of save and restore
operations for EL1 context:
MDCCINT_EL1
MDSCR_EL1
DISR_EL1
PIRE0_EL1
fix(cm): add more system registers to EL1 context mgmt
The following system registers are made part of save and restore
operations for EL1 context:
MDCCINT_EL1
MDSCR_EL1
DISR_EL1
PIRE0_EL1
PIR_EL1
POR_EL1
S2POR_EL1
TCR2_EL1
Some of these registers are available as part of core Armv8-A
architecture while others are made available through various
architectural extensions.
Change-Id: I507dccb9053ba177e1b98100fceccd1f32bdfc5c
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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| d594ace6 | 20-Mar-2024 |
Harrison Mutai <harrison.mutai@arm.com> |
fix(handoff): correct representation of tag_id
The tag ID is a 3-byte field used to identify the contents of a TE. In
our library, the internal representation of the tag is a 2 byte field.
We curren
fix(handoff): correct representation of tag_id
The tag ID is a 3-byte field used to identify the contents of a TE. In
our library, the internal representation of the tag is a 2 byte field.
We currently ignore the top byte of this field, marking it res0. This
causes problems when dealing with non-standard TE types, whose range
starts at 0xff_f000. This commit fixes this by using a bit-field with a
24-bit width, and packing `transfer_list_entry`.
Change-Id: Ib3c212f964b64f528ad6f3dd6ab8b4597b877cd9
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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| a77459dc | 03-Apr-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(handoff): add additional TE tags" into integration |
| 0f4811b4 | 02-Apr-2024 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes I3a4f9a4f,Iedc4e640 into integration
* changes:
docs(rmm): document console struct in rmm boot manifest
feat(rme): pass console info via RMM-EL3 ifc |
| a312bfb3 | 01-Dec-2023 |
Harrison Mutai <harrison.mutai@arm.com> |
feat(handoff): add additional TE tags
`TL_TAG_EXEC_EP_INFO64` type entries represent the `entry_point_info_t`
data structure. This structure provides the consumer with the execution
environment of a
feat(handoff): add additional TE tags
`TL_TAG_EXEC_EP_INFO64` type entries represent the `entry_point_info_t`
data structure. This structure provides the consumer with the execution
environment of an image. This is needed primarily in BL31 to execute
subsequent images i.e. BL32, BL33, or NT FW.
`TL_TAG_DT_SPMC_MANIFEST` holds the SPMC (Secure Partition Manager Core)
manifest image which is in DT format.
Change-Id: I80c4a72d639851457bc3c9b158b2e56041e8b29a
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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| 32904472 | 26-Mar-2024 |
Soby Mathew <soby.mathew@arm.com> |
feat(rme): pass console info via RMM-EL3 ifc
This patch modifies the boot manifest to add console information to
be passed from EL3 to RMM.
Boot manifest version is bumped to v0.3
Signed-off-by: H
feat(rme): pass console info via RMM-EL3 ifc
This patch modifies the boot manifest to add console information to
be passed from EL3 to RMM.
Boot manifest version is bumped to v0.3
Signed-off-by: Harry Moulton <harry.moulton@arm.com>
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: Iedc4e640fb7a4450ce5ce966ae76936d1b7b742d
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| 67ff4f56 | 28-Mar-2024 |
Leo Yan <leo.yan@arm.com> |
refactor(arm): remove unused SP_MIN UART macros
Currently, tf-a has been refactored to support the multi UARTs (boot and
runtime UARTs). As a result, the SP_MIN UART related code has been
removed, a
refactor(arm): remove unused SP_MIN UART macros
Currently, tf-a has been refactored to support the multi UARTs (boot and
runtime UARTs). As a result, the SP_MIN UART related code has been
removed, and the macros are no longer used.
Therefore, this patch removes these unused UART macros.
Change-Id: I496349f876ba918fcafa7ed6c65d149914762290
Signed-off-by: Leo Yan <leo.yan@arm.com>
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