feat(gicv3): add GIC-720AE model id

Add GIC-720AE model id to power up its Redistributor in BL31 GIC
initialization.
No use case so far for multichip support on GIC-720AE.

Change-Id: Id6ca8144b0c02

feat(gicv3): add GIC-720AE model id

Add GIC-720AE model id to power up its Redistributor in BL31 GIC
initialization.
No use case so far for multichip support on GIC-720AE.

Change-Id: Id6ca8144b0c02557ba7569a536cece37e4c1fe98
Signed-off-by: David Hu <david.hu2@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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feat(guid-partition): platform hook to log corrupted GPT

Notification of the GPT corruption can be beneficial,
using the handoff structure from BL2 to
BL32 for logging the GPT corruption information

feat(guid-partition): platform hook to log corrupted GPT

Notification of the GPT corruption can be beneficial,
using the handoff structure from BL2 to
BL32 for logging the GPT corruption information

Change-Id: Ie1af7eb6d97ec76f3f6d1cffad292782bdedda21
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge "feat(mbedtls): update mbedtls to version 3.6.4" into integration

Merge "refactor(el3-runtime): move context security states to context.h" into integration

feat(lfa): add platform hook for activation notification

Introduce a new platform API, plat_lfa_notify_activate(), which allows
the platform to notify its security engine to begin component
activati

feat(lfa): add platform hook for activation notification

Introduce a new platform API, plat_lfa_notify_activate(), which allows
the platform to notify its security engine to begin component
activation. The function accepts a component identifier and should
return 0 on success or an error code on failure.

Documentation and header files are updated accordingly, and the call is
integrated into the LFA activation path.

Change-Id: Ic66aa675bba62633cc92992b965d144a6f9ef129
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(mbedtls): update mbedtls to version 3.6.4

In order to successfully update mbedtls to version 3.6.4, the
redundant-decls warning must be disabled to accomodate a change in the
definition locatio

feat(mbedtls): update mbedtls to version 3.6.4

In order to successfully update mbedtls to version 3.6.4, the
redundant-decls warning must be disabled to accomodate a change in the
definition locations of some helper functions. This is currently an open
issue for mbedtls: https://github.com/Mbed-TLS/mbedtls/issues/10376

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I57c9c14aabe75a51c74dcf2a33faf59f95ce2386

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fix(cm): remove unused macro

It is never referenced.

Change-Id: I538b1f3d8660426faf5bafa68ecda2d637b0bc50
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

refactor(arm/common): gate coherency behind flag

Introduce a macro guard so platform coherency functions are only
compiled when HW_ASSISTED_COHERENCY is 0 (disabled). Many platforms
enable HW-assist

refactor(arm/common): gate coherency behind flag

Introduce a macro guard so platform coherency functions are only
compiled when HW_ASSISTED_COHERENCY is 0 (disabled). Many platforms
enable HW-assisted coherency by default, so compiling empty
definitions is unnecessary.

This refactor removes those empty functions for Arm CSS platforms.

Change-Id: I102ead46960e9da2d8b968f60cbfd3e5e5da1096
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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Merge "refactor(el3-runtime): extract cpu_data limitations to top-level constraints" into integration

fix(arm): don't override the gic redistributor frames

Patch 75170704c made an oversight - it would provide a default value for
the gicr_frames variable but would always set to it, regardless of
whet

fix(arm): don't override the gic redistributor frames

Patch 75170704c made an oversight - it would provide a default value for
the gicr_frames variable but would always set to it, regardless of
whether the platform might want to use something different. The thinking
was to provide a default and then let each platform override it, however
the order was swapped.

To fix this, put the gic_set_gicr_frames() in bl31_platform_setup()
rather than arm_bl31_platform_setup(). This way, platforms that use the
default can still enjoy it automatically pulled in from common code,
platforms that need fully custom gicr_frames can simply set it, and
platforms that override bl31_platform_setup() for unrelated reasons only
have to redo the call to gic_set_gicr_frames(). This has a tiny benefit
over the old approach in that there will never be 2 gicr_frames arrays.

Change-Id: I734737d3bd37ddbb3286abcdd92c88676c68cdc3
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): enable FEAT_CPA2 for EL3

FEAT_CPA2 enables checked pointer arithmetic, which in the event
of an arithmetic overflow in pointer generation will result in a
non-canonical pointer being

feat(cpufeat): enable FEAT_CPA2 for EL3

FEAT_CPA2 enables checked pointer arithmetic, which in the event
of an arithmetic overflow in pointer generation will result in a
non-canonical pointer being generated and subsequent address fault.

Note that FEAT_CPA is a trivial implementation that exists in
some hardware purely so it can run CPA2-enabled instructions
without crashing but they don't actually have checked arithmetic,
so FEAT_CPA is not explicitly enabled in TF-A.

Change-Id: I6d2ca7a7e4b986bb9e917aa8baf8091a271c168b
Signed-off-by: John Powell <john.powell@arm.com>

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feat(arm): handle RMM ep_info during LFA

Update the logic for next image handoff to correctly manage the
RMM entry point information when LFA is in progress.
This ensures control is passed back into

feat(arm): handle RMM ep_info during LFA

Update the logic for next image handoff to correctly manage the
RMM entry point information when LFA is in progress.
This ensures control is passed back into RMM during the
activation sequence.

This change only affects during LFA run, normal boot behavior
is unchanged.

Change-Id: I8f85e9a7e0a7e9dab196c69ecf55abb9e7717982
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(lfa): add helper to check LFA prime completion status

Introduce `is_lfa_prime_finished()` to allow callers to query whether the
prime operation for a given component has completed. This enables

feat(lfa): add helper to check LFA prime completion status

Introduce `is_lfa_prime_finished()` to allow callers to query whether the
prime operation for a given component has completed. This enables external
logic to safely determine if activation is ready to proceed.

The helper checks for:
- Matching `component_id` in the current activation
- Prime status being `PRIME_COMPLETE`
- `activation_pending` being true

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I55dadba639571faacc27de245cf0a9f2493956a5

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chore(lfa): use standard int return type for prime/activate callbacks

Replace `int32_t` with `int` for `component_prime_fn` and
`component_activate_fn` typedefs, along with their implementations
in

chore(lfa): use standard int return type for prime/activate callbacks

Replace `int32_t` with `int` for `component_prime_fn` and
`component_activate_fn` typedefs, along with their implementations
in BL31 and RMM LFA services. This aligns with common convention
for function return types and avoids unnecessary use of fixed-width
types where a native int is sufficient

Change-Id: Id22e93a554260b22e36b59baeac2cbb1b4646727
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(rmmd): add warm reset helpers for primary and secondary CPUs

Introduce two helpers to support RMM warm reset, primarily for use
during Live Firmware Activation:

- rmmd_primary_warm_reset(): r

feat(rmmd): add warm reset helpers for primary and secondary CPUs

Introduce two helpers to support RMM warm reset, primarily for use
during Live Firmware Activation:

- rmmd_primary_warm_reset(): re-runs rmmd_setup() and rmm_init()
for the primary CPU.
- rmmd_secondary_warm_reset(): reinitializes secondary CPUs using
rmmd_cpu_on_finish_handler(), with a spinlock to serialize
access.

Change-Id: I885536aa85e395ed69069802112dcdb5063a9c19
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge changes I2c7c8da9,I9786ab88,Ia76ba243,Ifec40dee,Ifdd59c09, ... into integration

* changes:
fix(cpus): workaround for Cortex-A510 erratum 3704847
fix(cpus): workaround for Cortex-A510 errat

Merge changes I2c7c8da9,I9786ab88,Ia76ba243,Ifec40dee,Ifdd59c09, ... into integration

* changes:
fix(cpus): workaround for Cortex-A510 erratum 3704847
fix(cpus): workaround for Cortex-A510 erratum 3672349
fix(cpus): workaround for Cortex-A510 erratum 2420992
fix(cpus): workaround for Cortex-A510 erratum 2218134
fix(cpus): workaround for Cortex-A510 erratum 2169012
fix(cpus): workaround for Cortex-A510 erratum 2008766

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refactor(el3-runtime): streamline cpu_data assembly offsets using the cpu_ops template

The cpu_data structure, just like cpu_ops, is collection of disparate
data that must be accessible from both C

refactor(el3-runtime): streamline cpu_data assembly offsets using the cpu_ops template

The cpu_data structure, just like cpu_ops, is collection of disparate
data that must be accessible from both C and assembly. Achieving this is
tricky as there is no way to export structure offsets from C directly so
they must be manually recreated with `#define`s and asserts. However,
the cpu_data structure is quite old and the assembly offsets are a
patchwork of additions and extremely difficult to reason with and
modify. In fact, certain currently unused builds with
ENABLE_RUNTIME_INSTRUMENTATION=1 fail to build.

To untangle this, convert the assembly offsets to the pattern used for
the cpu_ops structure. That is, first define the sizes of every member,
as generically as possible, and then chain their offsets one after the
other. To make sure this is always correct, add a CASSERT for the offset
of every member. This makes it easy to modify the structure and fixes
the build failures.

Change-Id: I61aeb55e9c494896663a3c719c10e3c072f56349
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix: remove unused cpu_data related macros

There are no uses for CPU_DATA_PSCI_LOCK_OFFSET so it is removed.

PLAT_PCPU_DATA_SIZE is also unused in ST platforms and causes offsets
to mismatch when t

fix: remove unused cpu_data related macros

There are no uses for CPU_DATA_PSCI_LOCK_OFFSET so it is removed.

PLAT_PCPU_DATA_SIZE is also unused in ST platforms and causes offsets
to mismatch when the linker garbage collects it. It is also removed.

CPU_DATA_PLAT_PCPU_OFFSET is also removed as its only use is in
rcar_lock_get() and related macros which are never called since all
calls of these macros lack an argument.

Change-Id: I883ab58c56b4082e0e8b19a8d8f6186945bcc58e
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(el3-runtime): move context security states to context.h

The three security states (S, NS, RL) are architecturally quite
consistent - anything that uses them has the same numerical assignmen

refactor(el3-runtime): move context security states to context.h

The three security states (S, NS, RL) are architecturally quite
consistent - anything that uses them has the same numerical assignments
(0, 1, 2) and they are quite convenient for indexing. However, we're not
as consistent in tf-a and this is defined in a few places. Since
cpu_data has a dependency on the context management library, use its
security state convention in a few more places and take away this
responsibility from cpu_data.

Change-Id: Iec73b2be2eef91975554767557de72424d0031f1
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(el3-runtime): extract cpu_data limitations to top-level constraints

CRASH_REPORTING is checked via an `#error` statement in the header,
while EL3_EXCEPTION_HANDLING is carefully carved out

refactor(el3-runtime): extract cpu_data limitations to top-level constraints

CRASH_REPORTING is checked via an `#error` statement in the header,
while EL3_EXCEPTION_HANDLING is carefully carved out when not supported.
However, both are only used on AArch64 builds and never on AArch32. We
can promote both to proper make constraints and keep the cpu_data
implementation a little bit simpler.

Change-Id: Ia164e046f953a552dc6e6cf624961a90669eaeeb
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "ja/ffa_v1_3" into integration

* changes:
feat(tc): bump SPMC version to FF-A v1.3 TC platform
feat(fvp): bump the SPMC version
feat(ff-a): bump SPMD FF-A version

fix(cpus): workaround for Cortex-A510 erratum 3672349

Cortex-A510 erratum 3672349 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3, r1p0, r1p1, r1p2 and r1p3, and
is still open.

fix(cpus): workaround for Cortex-A510 erratum 3672349

Cortex-A510 erratum 3672349 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3, r1p0, r1p1, r1p2 and r1p3, and
is still open.

The workaround is to clear the WFE_RET_CTRL and WFI_RET_CTRL fields
in CPUPWRCTLR_EL1 to disable full retention.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1873361/latest/

Change-Id: I9786ab8843a2eab45e650c6af50b6933481527ec
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-A510 erratum 2420992

Cortex-A510 erratum 2420992 is a Cat B erratum that applies only to
revisions r1p0 and r1p1, and is fixed in r1p1.

The workaround is to set bit

fix(cpus): workaround for Cortex-A510 erratum 2420992

Cortex-A510 erratum 2420992 is a Cat B erratum that applies only to
revisions r1p0 and r1p1, and is fixed in r1p1.

The workaround is to set bit 3 in CPUACTLR3_EL1 which will have no
performance impact, but will increase power consumption by 0.3-0.5%.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1873361/latest/

Change-Id: Ia76ba2431d76f14c08b95a998806986190d682c3
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-A510 erratum 2218134

Cortex-A510 erratum 2218134 is a Cat B erratum that applies only to
revision r1p0 and is fixed in r1p1.

The workaround is to set bit 43 in CPUA

fix(cpus): workaround for Cortex-A510 erratum 2218134

Cortex-A510 erratum 2218134 is a Cat B erratum that applies only to
revision r1p0 and is fixed in r1p1.

The workaround is to set bit 43 in CPUACTLR2_EL1 which will correct
the instruction fetch stream with no performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1873361/latest/

Change-Id: Ifec40dee2f7e42c56c9ed447b6b1997b170f9453
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cm): deprecate use of NS_TIMER_SWITCH

On AArch64, secure world has it's own EL3 physical timer registers
accessible to secure EL1 in absence of S-EL2. With S-EL2 there is
virtualized view availa

fix(cm): deprecate use of NS_TIMER_SWITCH

On AArch64, secure world has it's own EL3 physical timer registers
accessible to secure EL1 in absence of S-EL2. With S-EL2 there is
virtualized view available for EL1 timer registers. So it is
unreasonable for secure world to use non-secure EL1 physical timer
registers. Moreover, the non-secure operating system (Linux in our case)
relies heavily on these EL1 physical timer registers for scheduling
decisions. If NS_TIMER_SWITCH is enabled, it simply breaks the preemption
model of the non-secure world by disabling non-secure timer interrupts
leading to RCU stalls being observed on long running secure world tasks.

The only arch timer register which will benefit from context management
is cntkctl_el1: Counter-timer Kernel Control Register. This enables the
secure and non-secure worlds to independently control accesses to EL0
for counter-timer registers. This is something that OP-TEE uses to
enable ftrace feature for Trusted Applications and SPM_MM uses for EL0
access as well.

Lets enable context management of cntkctl_el1 by default and deprecate
conditional context management of non-secure EL1 physical timer
registers for whom there isn't any upstream user. With that deprecate
this NS_TIMER_SWITCH build option which just adds confusion for the
platform maintainers. It will be eventually dropped following
deprecation policy of TF-A.

Reported-by: Stauffer Thomas MTANA <thomas.stauffer@mt.com>
Reported-by: Andrew Davis <afd@ti.com>
Change-Id: Ifb3a919dc0bf8c05c38895352de5fe94b4f4387e
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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