fix(el3-spmc): fixed x8-x17 register handling for FFA 1.2

Changed spmd_smc_switch_state to return all 18 registers for 64 bit
calls, and set x8-17 to zero if necessary.

BREAKING CHANGE: Zeroes or f

fix(el3-spmc): fixed x8-x17 register handling for FFA 1.2

Changed spmd_smc_switch_state to return all 18 registers for 64 bit
calls, and set x8-17 to zero if necessary.

BREAKING CHANGE: Zeroes or forwards a different set of registers,
depending on the FF-A version of the source and destination.
E.g. a call from a v1.1 caller to a v1.2 destination will zero
out the extended registers, which is different from the old behavior
of forwarding everything to EL2 SPMC, but only x0-x7 to the EL3 SPMC.

Change-Id: Ic31755af0fbb117b0ed74565fba9decebab353c4
Signed-off-by: Jay Monkman <jmonkman@google.com>
Signed-off-by: Andrei Homescu <ahomescu@google.com>

show more ...

fix(console): ensured proper bitwise shift operation

This corrects the MISRA violation C2012-12.2:
Used BIT_32() rather than manual bit shifting to prevent shifting
beyond the essential type width o

fix(console): ensured proper bitwise shift operation

This corrects the MISRA violation C2012-12.2:
Used BIT_32() rather than manual bit shifting to prevent shifting
beyond the essential type width of the left operand. This ensures
compliance with MISRA C 2012 Rule 12.2.

Change-Id: I1a4ed9366bd9ab773c4a5f6798508ead991593d2
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

show more ...

Merge "feat(smccc): introduce TPM Start SMC" into integration

feat(cpufeat): add support for FEAT_FGWTE3

Enable write traps for key EL3 system registers as per FEAT_FGWTE3,
ensuring their values remain unchanged after boot.

Excluded Registers:
MDCR_EL3 and MP

feat(cpufeat): add support for FEAT_FGWTE3

Enable write traps for key EL3 system registers as per FEAT_FGWTE3,
ensuring their values remain unchanged after boot.

Excluded Registers:
MDCR_EL3 and MPAM3_EL3: Not trapped as they are part of the EL3 context.
SCTLR_EL3: Not trapped since it is overwritten during
powerdown sequence(Included when HW_ASSISTED_COHERENCY=1)

TPIDR_EL3: Excluded due to its use in crash reporting(It is included
when CRASH_REPORTING=0)

Reference:
https://developer.arm.com/documentation/ddi0601/2025-06/AArch64-Registers/FGWTE3-EL3--Fine-Grained-Write-Traps-EL3

Change-Id: Idcb32aaac7d65a0b0e5c90571af00e01a4e9edb1
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>

show more ...

feat(smccc): introduce TPM Start SMC

To support TPM start method compatible with pre-FFA configuration (to
support SPM_MM) introduce an SMC FID el3 vendor specific range. This
SMC is forwarded to SP

feat(smccc): introduce TPM Start SMC

To support TPM start method compatible with pre-FFA configuration (to
support SPM_MM) introduce an SMC FID el3 vendor specific range. This
SMC is forwarded to SPM_MM module which converts into a MM_COMMUNICATE
to interact with Secure partition.

TPM Start method is mentioned in TCG ACPI spec section 3.3.1
https://trustedcomputinggroup.org/wp-content/uploads/TCG-ACPI-Specification-Version-1.4-Revision-15_pub.pdf

As this patch introduces a new sub service, increment minor version
of Vendor EL3 service.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I61698018e6bc33c9b389ac905fe158810af21bfa

show more ...

fix(el3-runtime): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or o

fix(el3-runtime): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
Replaced usage of 'unsigned int' with 'size_t' to ensure type
consistency and prevent assignment to a narrower or different
essential type.

Change-Id: I79501e216a04753ebd005d64375357b9332440d9
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

show more ...

fix(arm): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a diff

fix(arm): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: I7a2565ce6b8beb71dc9c711327ab72ce825111cc
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

show more ...

Merge "feat(locks): add non-blocking spinlock_try() API" into integration

refactor(cm): gather per-world context management to the same place

The per-world calls are disparate - they get called in different places,
are guarded in different ways, and the code is apart.

Si

refactor(cm): gather per-world context management to the same place

The per-world calls are disparate - they get called in different places,
are guarded in different ways, and the code is apart.

Since they just need to be called once at boot, add a function that we
can call from BL31 and be done with it.

Change-Id: Id0ade302e35f2b00ca37c552a53038942ab7b58e
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

feat(lib): add mmio read with timeout

In several cases, drivers poll a register using a blocking 'while'
or 'for' loop without a timeout mechanism. Introducing a timeout
would be beneficial, as it a

feat(lib): add mmio read with timeout

In several cases, drivers poll a register using a blocking 'while'
or 'for' loop without a timeout mechanism. Introducing a timeout
would be beneficial, as it allows the system to log an error and
delegate the decision to the caller - whether to continue execution
or halt with a panic.

To address this, the mmio_read_poll_timeout() helper can be used. It
exits with -ETIMEDOUT if the timeout is reached, or 0 on success.
Additionally, the final value read from the register is stored in the
'val' variable, avoiding the need for an extra read after polling
completes.

Change-Id: I2ef53299b12ece6bc7be0e1234d5c2708e36ecf9
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

show more ...

Merge "build(handoff)!: switch to LibTL submodule" into integration

Merge "feat(dsu): support power control and autonomous powerdown config" into integration

fix(common): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a d

fix(common): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: I350ba1dfd1af872c6d237aa7b46221fc10a2ef67
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

show more ...

Merge changes Iea4c11de,Icae1fb08 into integration

* changes:
fix(lx2160): add DDRC missing DIMMs
fix(nxp): driver crypto caam

Merge "fix(libc): replace true-false with explicit comparisons" into integration

feat(dsu): support power control and autonomous powerdown config

This patch allows platforms to enable certain DSU settings
to ensure memory retention and control over
cache power requests. We also

feat(dsu): support power control and autonomous powerdown config

This patch allows platforms to enable certain DSU settings
to ensure memory retention and control over
cache power requests. We also move the driver out of css
into drivers/arm. Platforms can configure the
CLUSTERPWRCTLR and CLUSTERPWRDN registers [1] to improve
power efficiency.

These registers enable finer-grained control of
DSU power state transitions, including
powerdown and retention.

IMP_CLUSTERPWRCTLR_EL1 provides:
- Functional retention: Allows configuration of the
duration of inactivity before the DSU uses
CLUSTERPACTIVE to request functional retention.

- Cache power request: These bits are output on
CLUSTERPACTIVE[19:16] to indicate to the power controller
which cache portions must remain powered.

IMP_CLUSTERPWRDN_EL1 includes:
- Powerdown: Triggers full cluster powerdown, including
control logic.

- Memory retention: Requests memory retention mode,
keeping L3 RAM contents while powering off
the rest of the DSU.

The DSU-120 TRM [2] provides the full field definitions,
which are used as references in the `dsu_driver_data` structure.

References:
[1]: https://developer.arm.com/documentation/100453/latest/
[2]: https://developer.arm.com/documentation/102547/0201/?lang=en

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I2eba808b8f2a27797782a333c65dd092b03208fe

show more ...

build(handoff)!: switch to LibTL submodule

Removes in-tree Transfer List implementation and updates all references
to use the external LibTL submodule. Updates include paths, Makefile
macros, and pl

build(handoff)!: switch to LibTL submodule

Removes in-tree Transfer List implementation and updates all references
to use the external LibTL submodule. Updates include paths, Makefile
macros, and platform integration logic to link with LibTL as a static
library.

If you cloned TF-A without the `--recurse-submodules` flag, you can
ensure that this submodule is present by running:

git submodule update --init --recursive

BREAKING-CHANGE: LibTL is now included in TF-A as a submodule.
Please run `git submodule update --init --recursive` if you encounter
issues after migrating to the latest version of TF-A.

Change-Id: I1fa31f7b730066c27985d968698e553b00b07c38
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

show more ...

Merge changes from topic "mb/lfa-core-work" into integration

* changes:
docs(maintainers): add myself as code owner for LFA service
docs(lfa): update porting guide with LFA platform APIs
feat(

Merge changes from topic "mb/lfa-core-work" into integration

* changes:
docs(maintainers): add myself as code owner for LFA service
docs(lfa): update porting guide with LFA platform APIs
feat(lfa): add LFA holding pen logic
feat(lfa): add initial implementation for LFA_ACTIVATE
feat(lfa): add initial implementation for LFA_PRIME
feat(fvp): implement platform API for load and auth image
feat(lfa): implement LFA_CANCEL SMC
feat(fvp): implement platform API for LFA cancel operation
feat(lfa): implement LFA_GET_INVENTORY SMC
feat(fvp): implement platform API for LFA activation pending check
feat(lfa): implement LFA_GET_INFO SMC and integrate LFA build
feat(fvp): initialize LFA component activators in platform layer
feat(rmm): add placeholder activator callbacks for LFA
feat(bl31): add placeholder activator implementation for LFA
feat(lfa): add activation handler interface for component activation
feat(fvp): implement LFA get components API
feat(lfa): create LFA SMC handler template

show more ...

Merge changes from topic "s32g274a/sd_support" into integration

* changes:
feat(s32g274a): move fip in a dedicated partition
feat(s32g274ardb): initialize the IO buffer
feat(s32g274ardb): init

Merge changes from topic "s32g274a/sd_support" into integration

* changes:
feat(s32g274a): move fip in a dedicated partition
feat(s32g274ardb): initialize the IO buffer
feat(s32g274ardb): initialize the uSDHC driver
feat(s32g274ardb): set the system counter rate
feat(s32g274ardb): init the generic timer for BL2
fix(nxp-mmc): handle response for CMD0
refactor(mmc): replace 0 with MMC_RESPONSE_NONE
feat(mmc): add define for no response

show more ...

feat(lfa): add LFA holding pen logic

Add LFA holding logic to be used by the LFA activate SMC call to manage
CPU rendezvous. All CPUs are expected to invoke the LFA activate call
for the rendezvous,

feat(lfa): add LFA holding pen logic

Add LFA holding logic to be used by the LFA activate SMC call to manage
CPU rendezvous. All CPUs are expected to invoke the LFA activate call
for the rendezvous, until then, they will remain on a holding lock.
When the final CPU calls LFA activate, it will release the holding
lock after completing the activation process on that CPU, allowing
the activation process on secondary CPUs to proceed.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Iff9e40dd87420245fe5844e286d0685c1f0db289

show more ...

feat(lfa): add initial implementation for LFA_ACTIVATE

This patch introduces the overall handling of the LFA_ACTIVATE call,
including input validation and invocation flow.
While this covers the core

feat(lfa): add initial implementation for LFA_ACTIVATE

This patch introduces the overall handling of the LFA_ACTIVATE call,
including input validation and invocation flow.
While this covers the core implementation, per-component-specific
handling will be developed in a separate patch. The respective
component callbacks are invoked as part of this logic.

Change-Id: Ie9d4584fc0c0abc9a9faffed62165b4461efed3a
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

show more ...

feat(lfa): add initial implementation for LFA_PRIME

This patch introduces the overall handling of the LFA_PRIME call,
including input validation and invocation flow.
While this covers the core imple

feat(lfa): add initial implementation for LFA_PRIME

This patch introduces the overall handling of the LFA_PRIME call,
including input validation and invocation flow.
While this covers the core implementation, per-component-specific
handling will be developed in a separate patch. The respective
component callbacks are invoked as part of this logic.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ie13d15d0a060ae5f9704991245d2a65c7d846047

show more ...

feat(fvp): implement platform API for load and auth image

Introduce and implement a stub implementation of
`plat_lfa_load_auth_image()` for the FVP platform. For AEM FVP, no
actual image loading or

feat(fvp): implement platform API for load and auth image

Introduce and implement a stub implementation of
`plat_lfa_load_auth_image()` for the FVP platform. For AEM FVP, no
actual image loading or authentication is required as of now, as
images are assumed to be pre-loaded and authenticated.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I82e51f5d18db6d5b9c61f9081b451619d761abe8

show more ...

feat(fvp): implement platform API for LFA cancel operation

Introduce and implement a stub implementation of `plat_lfa_cancel()`
for the FVP platform. This function will later be expanded to handle
c

feat(fvp): implement platform API for LFA cancel operation

Introduce and implement a stub implementation of `plat_lfa_cancel()`
for the FVP platform. This function will later be expanded to handle
component-specific LFA cancellation logic.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I9690b011313bbe0fd458cbe47f32445f8d2d79fa

show more ...

feat(lfa): implement LFA_GET_INVENTORY SMC

This implementation primarily retrieves activation-related flags for
a given fw_seq_id, including whether the firmware is activation
capable, whether an up

feat(lfa): implement LFA_GET_INVENTORY SMC

This implementation primarily retrieves activation-related flags for
a given fw_seq_id, including whether the firmware is activation
capable, whether an update is pending activation, whether it resets
the CPU during activation, whether CPU rendezvous is required, and the
firmware's UUID.
To support this, a platform API is called to determine whether an
update is available for the specified fw_seq_id, indicating its
pending activation status.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I6e702a8b313386f5668027386845ff2dae9328e7

show more ...