| b57d9d6f | 20-Jan-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "new_ls1043a" into integration
* changes:
docs(maintainers): update nxp layerscape maintainers
docs(plat/nxp/layerscape): add ls1043a soc and board support
feat(plat/n
Merge changes from topic "new_ls1043a" into integration
* changes:
docs(maintainers): update nxp layerscape maintainers
docs(plat/nxp/layerscape): add ls1043a soc and board support
feat(plat/nxp/ls1043ardb): add ls1043ardb board support
feat(plat/nxp/ls1043a): add ls1043a soc support
refactor(plat/ls1043): remove old implementation for platform ls1043
feat(nxp/driver/dcfg): add some macro definition
fix(nxp/common/setup): increase soc name maximum length
feat(nxp/common/errata): add SoC erratum a008850
feat(nxp/driver/tzc380): add tzc380 platform driver support
feat(tzc380): add sub-region register definition
feat(nxp/common/io): add ifc nor and nand as io devices
feat(nxp/driver/ifc_nand): add IFC NAND flash driver
feat(nxp/driver/ifc_nor): add IFC nor flash driver
feat(nxp/driver/csu): add bypass bit mask definition
feat(nxp/driver/dcfg): add gic address align register definition
feat(nxp/common/rcpm): add RCPM2 registers definition
fix(nxp/common/setup): fix total dram size checking
feat(nxp/common): add CORTEX A53 helper functions
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| 1b29fe53 | 21-Oct-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(nxp/driver/dcfg): add some macro definition
Added offset for register DEVDISR2 and DEVDISR3, added
bit definiton for PORSR1_RCW, and some macro for SVR.
Signed-off-by: Jiafei Pan <Jiafei.Pan@n
feat(nxp/driver/dcfg): add some macro definition
Added offset for register DEVDISR2 and DEVDISR3, added
bit definiton for PORSR1_RCW, and some macro for SVR.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ie49392b89280c6c2c3510fcb4c85d827a1efdac0
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| de9e57ff | 21-Oct-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(nxp/driver/tzc380): add tzc380 platform driver support
Added TZC380 platform driver support.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Id0aa6cb64fa7af79dd44e0dbb0e62cb2fd4cb824 |
| fdafe2b5 | 21-Oct-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(tzc380): add sub-region register definition
Added sub-region register definition.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Iab8130b56089d804c51ab967b184ddfc192e2858 |
| 28279cf2 | 21-Oct-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(nxp/driver/ifc_nand): add IFC NAND flash driver
Support IFC NAND flash as boot device.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Chang
feat(nxp/driver/ifc_nand): add IFC NAND flash driver
Support IFC NAND flash as boot device.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I1aba7035ff70b179915e181c04e7b00be2066abe
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| e2fdc77b | 21-Oct-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(nxp/driver/ifc_nor): add IFC nor flash driver
Add IFC Nor flash driver.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I3275664b8848d0fe3c15ed92d95fb19adbf57f84 |
| ec5fc501 | 21-Oct-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(nxp/driver/csu): add bypass bit mask definition
Add TZASC_BYPASS_MUX_DISABLE definition.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ife4d819e2af6deb5e027491d30f6b7c5f79764e7 |
| 3a8c9d78 | 21-Oct-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(nxp/driver/dcfg): add gic address align register definition
Add some register fields definition.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I9fd78c318b34a2becd82d502fa6d18c8298e
feat(nxp/driver/dcfg): add gic address align register definition
Add some register fields definition.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I9fd78c318b34a2becd82d502fa6d18c8298eb40a
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| b208e3da | 15-May-2020 |
Gabriel Fernandez <gabriel.fernandez@st.com> |
refactor(st-clock): directly use oscillator name
Instead of transmitting an 'enum stm32mp_osc_id', just send
directly the clock name with a 'const char *'
Change-Id: I866b05cbb1685a9b9f80e63dcd5ba7
refactor(st-clock): directly use oscillator name
Instead of transmitting an 'enum stm32mp_osc_id', just send
directly the clock name with a 'const char *'
Change-Id: I866b05cbb1685a9b9f80e63dcd5ba7b1d35fc932
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
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| 8bbb1d80 | 21-Oct-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(cpu/cortex_a53): add L1PCTL macro definiton for CPUACTLR_EL1
Add L1PCTL field definiton in register CPUACTLR_EL1.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Iebfb240ac58aa8f3dc8
feat(cpu/cortex_a53): add L1PCTL macro definiton for CPUACTLR_EL1
Add L1PCTL field definiton in register CPUACTLR_EL1.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Iebfb240ac58aa8f3dc870804bf4390dfbdfa9b95
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| 0aa0b3af | 16-Dec-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(measured-boot): avoid Measured-Boot dependency on Trusted-Boot
Measured-Boot and Trusted-Boot are orthogonal to each other and hence
removed dependency of Trusted-Boot on Measured-Boot by m
refactor(measured-boot): avoid Measured-Boot dependency on Trusted-Boot
Measured-Boot and Trusted-Boot are orthogonal to each other and hence
removed dependency of Trusted-Boot on Measured-Boot by making below
changes -
1. BL1 and BL2 main functions are used for initializing Crypto module
instead of the authentication module
2. Updated Crypto module registration macro for MEASURED_BOOT with only
necessary callbacks for calculating image hashes
3. The 'load_auth_image' function is now used for the image measurement
during Trusted or Non-Trusted Boot flow
Change-Id: I3570e80bae8ce8f5b58d84bd955aa43e925d9fff
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 63d21598 | 02-Mar-2021 |
Nicolas Le Bayon <nicolas.le.bayon@foss.st.com> |
refactor(st-ddr): move basic tests in a dedicated file
These basic tests are generic and should be used independently of the
driver, depending on the plaftorm characteristics.
Change-Id: I38161b659
refactor(st-ddr): move basic tests in a dedicated file
These basic tests are generic and should be used independently of the
driver, depending on the plaftorm characteristics.
Change-Id: I38161b659ef2a23fd30a56e1c9b1bd98461a2fe4
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
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| 06e55dc8 | 18-May-2021 |
Nicolas Le Bayon <nicolas.le.bayon@st.com> |
refactor(st-ddr): reorganize generic and specific elements
stm32mp_ddrctl structure contains DDRCTRL registers definitions.
stm32mp_ddr_info contains general DDR information extracted from DT.
stm32
refactor(st-ddr): reorganize generic and specific elements
stm32mp_ddrctl structure contains DDRCTRL registers definitions.
stm32mp_ddr_info contains general DDR information extracted from DT.
stm32mp_ddr_size moves to the generic side.
stm32mp1_ddr_priv contains platform private data.
stm32mp_ddr_dt_get_info() and stm32mp_ddr_dt_get_param() allow to
retrieve data from DT. They are located in new generic c/h files in
which stm32mp_ddr_param structure is declared. Platform makefile
is updated.
Adapt driver with this new classification.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I4187376c9fff1a30e7a94407d188391547107997
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| 88f4fb8f | 17-Sep-2020 |
Yann Gautier <yann.gautier@st.com> |
feat(stm32mp1): allow configuration of DDR AXI ports number
A new flag STM32MP_DDR_DUAL_AXI_PORT is added, and enabled by default.
It will allow choosing single or dual AXI ports for DDR.
Change-Id
feat(stm32mp1): allow configuration of DDR AXI ports number
A new flag STM32MP_DDR_DUAL_AXI_PORT is added, and enabled by default.
It will allow choosing single or dual AXI ports for DDR.
Change-Id: I48826a66a6f4d18df87e081c0960af89ddda1b9d
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 5def13eb | 10-Sep-2021 |
Nicolas Le Bayon <nicolas.le.bayon@st.com> |
feat(st-ddr): add read valid training support
Add the read data eye training = training for optimal read valid placement
(RVTRN) when the built-in calibration is executed for LPDDR2 and LPDDR3.
Sig
feat(st-ddr): add read valid training support
Add the read data eye training = training for optimal read valid placement
(RVTRN) when the built-in calibration is executed for LPDDR2 and LPDDR3.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I7ac1c77c21ebc30315b532741f2f255c2312d5b2
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| 26cf5cf6 | 30-Apr-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
refactor(stm32mp1): remove the support of calibration result
The support of a predefined DDR PHY tuning result is removed for
STM32MP1 driver because it is not needed at the supported frequency
when
refactor(stm32mp1): remove the support of calibration result
The support of a predefined DDR PHY tuning result is removed for
STM32MP1 driver because it is not needed at the supported frequency
when built-in calibration is executed.
The calibration parameters were provided in the device tree by the
optional node "st,phy-cal", activated in ddr helper file by the
compilation flag DDR_PHY_CAL_SKIP and filled with values generated
by CubeMX.
This patch
- updates the binding file to remove "st,phy-cal" support
- updates the device trees and remove the associated defines
- simplifies the STM32MP1 DDR driver and remove the support of
the optional "st,phy-cal"
After this patch the built-in calibration is always executed.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I3fc445520c259f7f05730aefc25e64b328bf7159
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| 9565962c | 22-Dec-2020 |
Jona Stubbe <tf-a@jona-stubbe.de> |
refactor(plat/rockchip/rk3399/drivers/gpio): reduce code duplication
Refactor the GPIO code to use a small lookup table instead of redundant or
repetitive code.
Signed-off-by: Jona Stubbe <tf-a@jon
refactor(plat/rockchip/rk3399/drivers/gpio): reduce code duplication
Refactor the GPIO code to use a small lookup table instead of redundant or
repetitive code.
Signed-off-by: Jona Stubbe <tf-a@jona-stubbe.de>
Change-Id: Icf60385095efc1f506e4215d497b60f90e16edfd
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
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| e752fa4a | 01-Jan-2022 |
André Przywara <andre.przywara@arm.com> |
Merge "feat(allwinner): allow to skip PMIC regulator setup" into integration |
| 67412e4d | 01-Nov-2021 |
Andre Przywara <andre.przywara@arm.com> |
feat(allwinner): allow to skip PMIC regulator setup
For somewhat historical reasons we are doing some initial PMIC regulator
setup in BL31, as U-Boot does not (yet) have a PMIC driver. This worked
f
feat(allwinner): allow to skip PMIC regulator setup
For somewhat historical reasons we are doing some initial PMIC regulator
setup in BL31, as U-Boot does not (yet) have a PMIC driver. This worked
fine so far, but there is at least one board (OrangePi 3) that gets upset,
because the Ethernet PHY needs some *coordinated* bringup of *two*
regulators.
To avoid custom hacks, let's introduce a build option to keep doing the
regulator setup in TF-A. Defining SUNXI_SETUP_REGULATORS to 0 will break
support for some devices on some boards in U-Boot (Ethernet and HDMI),
but will allow to bring up the OrangePi 3 in Linux correctly. We keep
the default at 1 to not change the behaviour for all other boards.
After U-Boot gained proper PMIC support at some point in the future, we
will probably change the default to 0, to get rid of the less optimal
PMIC code in TF-A.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ie8e2583d0396f6eeaae8ffe6b6190f27db63e2a7
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| a006606f | 24-Dec-2021 |
Joanna Farley <joanna.farley@arm.com> |
Merge "feat(ccidx): update the do_dcsw_op function to support FEAT_CCIDX" into integration |
| 93b153b5 | 23-Dec-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "st_regulator" into integration
* changes:
feat(st-sdmmc2): manage cards power cycle
feat(stm32mp1): register fixed regulator
feat(st-drivers): introduce fixed regulat
Merge changes from topic "st_regulator" into integration
* changes:
feat(st-sdmmc2): manage cards power cycle
feat(stm32mp1): register fixed regulator
feat(st-drivers): introduce fixed regulator driver
refactor(st): update CPU and VDD voltage get
refactor(stm32mp1-fdts): update regulator description
refactor(st-pmic): use regulator framework for DDR init
feat(st-pmic): register the PMIC to regulator framework
refactor(st-pmic): split initialize_pmic()
feat(stm32mp1): add regulator framework compilation
feat(regulator): add a regulator framework
feat(stpmic1): add new services
feat(stpmic1): add USB OTG regulators
refactor(st-pmic): improve driver usage
refactor(stpmic1): set stpmic1_is_regulator_enabled() as boolean
refactor(stm32mp1): re-order drivers init
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| 0ca4b4b7 | 22-Dec-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "clock_framework" into integration
* changes:
feat(st): use newly introduced clock framework
feat(clk): add a minimal clock framework |
| 258bef91 | 10-May-2019 |
Yann Gautier <yann.gautier@st.com> |
feat(st-sdmmc2): manage cards power cycle
To correctly initialize the MMC devices, a power cycle is required.
For this we need to:
- disable vmmc-supply regulator
- make the power cycle required for
feat(st-sdmmc2): manage cards power cycle
To correctly initialize the MMC devices, a power cycle is required.
For this we need to:
- disable vmmc-supply regulator
- make the power cycle required for SDMMC2 peripheral
- enable regulators
Change-Id: I2be6d9082d1cc4c864a82cf2c31ff8522e2d31a2
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 5d6a2646 | 20-Jan-2021 |
Pascal Paillet <p.paillet@st.com> |
feat(st-drivers): introduce fixed regulator driver
Fixed regulator is mainly used when no pmic is available
Change-Id: Ib6a998684bcb055ba95a093bee563372d9051474
Signed-off-by: Pascal Paillet <p.pai
feat(st-drivers): introduce fixed regulator driver
Fixed regulator is mainly used when no pmic is available
Change-Id: Ib6a998684bcb055ba95a093bee563372d9051474
Signed-off-by: Pascal Paillet <p.paillet@st.com>
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| 85fb175b | 27-Sep-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
feat(st-pmic): register the PMIC to regulator framework
Register the PMIC to the regulator framework.
Change-Id: Ic825a8ef08505316db3dbd5944d62ea907f73c4a
Signed-off-by: Pascal Paillet <p.paillet@s
feat(st-pmic): register the PMIC to regulator framework
Register the PMIC to the regulator framework.
Change-Id: Ic825a8ef08505316db3dbd5944d62ea907f73c4a
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
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