| a00e9076 | 27-Jun-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
feat(cpus): add support for hermes cpu
Adding basic CPU library code to support the Hermes CPU.
Change-Id: I61946033fe5fafb56ceb2d14d4c796d85b30457e
Signed-off-by: Govindraj Raja <govindraj.raja@ar
feat(cpus): add support for hermes cpu
Adding basic CPU library code to support the Hermes CPU.
Change-Id: I61946033fe5fafb56ceb2d14d4c796d85b30457e
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| e7c0f42a | 22-Jun-2023 |
Juan Pablo Conde <juanpablo.conde@arm.com> |
refactor(fdt-wrappers): fix for unit testing errors
As the unit testing project uses the host machine GCC version to
compile, it is marking non-casted references as errors. This patch adds
the prope
refactor(fdt-wrappers): fix for unit testing errors
As the unit testing project uses the host machine GCC version to
compile, it is marking non-casted references as errors. This patch adds
the proper casting, so it compiles correctly for both Arm platforms and
host machines for unit testing.
Change-Id: Iee96e9117301ba28b6f164aac2cd36dc0f8b6be8
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
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| 6b6cefbf | 23-Jun-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "RAS_REFACTORING" into integration
* changes:
feat(board/rdn2): enable base element RAM RAS support on RD-N2 platform
feat(plat/arm): add memory map entry for CPER memor
Merge changes from topic "RAS_REFACTORING" into integration
* changes:
feat(board/rdn2): enable base element RAM RAS support on RD-N2 platform
feat(plat/arm): add memory map entry for CPER memory region
feat(plat/arm): firmware first error handling support for base RAMs
feat(plat/arm): update common platform RAS implementation
feat(plat/sgi): remove RAS setup call from common code
refactor(plat/sgi): deprecate DMC-620 RAS support
fix(plat/common): register PLAT_SP_PRI only if not already registered
fix(plat/sgi): update PLAT_SP_PRI macro definition
fix(plat/arm): add RAS_FFH_SUPPORT check for RAS EHF priority
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| 1c012840 | 22-Jun-2023 |
Omkar Anand Kulkarni <omkar.kulkarni@arm.com> |
fix(plat/arm): add RAS_FFH_SUPPORT check for RAS EHF priority
Define RAS EHF priority only if RAS_FFH_SUPPORT is enabled.
Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I01
fix(plat/arm): add RAS_FFH_SUPPORT check for RAS EHF priority
Define RAS EHF priority only if RAS_FFH_SUPPORT is enabled.
Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I0183a0af510337c8dfb9d12427541fa6c91bb4a5
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| 732af872 | 20-Jun-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "xlnx_zynqmp_sizefixes" into integration
* changes:
fix(zynqmp): type cast addresses to fix overflow issue
fix: integer suffix macro definition |
| 3a95b5d5 | 20-Jun-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(lib): implement memcpy_s in lib" into integration |
| 1a56ed4b | 08-Jun-2023 |
Akshay Belsare <akshay.belsare@amd.com> |
fix: integer suffix macro definition
The current implementation of macro L/LL/UL/ULL concatenates the input
with "L"/"LL"/"UL"/"ULL" respectively.
In the case where a macro is passed to L/LL/UL/ULL
fix: integer suffix macro definition
The current implementation of macro L/LL/UL/ULL concatenates the input
with "L"/"LL"/"UL"/"ULL" respectively.
In the case where a macro is passed to L/LL/UL/ULL as input,
the input macro name is concatenated with, rather than expanding
the input macro and then concatenating it.
The implementation of L/LL/UL/ULL is modified to two level macro,
so as to concatenate to the expansion of a macro argument.
Change 5b33ad174a0 "Unify type of "cpu_idx" across PSCI module."
has modified the implementation of U() to two level macros without
changing the implementation of other macros.
Change-Id: Ie93d67dff5ce96223a3faf6c98b98fcda530fc34
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
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| de7e3e9c | 16-Jun-2023 |
Manish Pandey <manish.pandey2@arm.com> |
chore(smccc): bump up SMCCC version to 1.4
TF-A code supports SMCCC spec version 1.4 while version is still kept
1.2. Bump up the version.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Chan
chore(smccc): bump up SMCCC version to 1.4
TF-A code supports SMCCC spec version 1.4 while version is still kept
1.2. Bump up the version.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ie5476c4601bd504d3f3e8433e1d672ebd0a758b1
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| d2e07436 | 15-Jun-2023 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes from topic "bk/errata_refactor" into integration
* changes:
feat(cpus): add more errata framework helpers
docs: document the errata framework |
| 94a75ad4 | 04-Apr-2023 |
Boyan Karatotev <boyan.karatotev@arm.com> |
feat(cpus): add more errata framework helpers
Figuring out the naming format of errata is annoying, so add a shorthand
for the custom checker functions. Also add some more semantic macros
instead of
feat(cpus): add more errata framework helpers
Figuring out the naming format of errata is annoying, so add a shorthand
for the custom checker functions. Also add some more semantic macros
instead of passing around constants.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ibdcf72146738026df4ebd047bfb30790fd4a1053
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| f328bff6 | 28-May-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
feat(lib): implement memcpy_s in lib
To support memcpy_s for better security purpose
to avoid overflowing the dest while copy from src.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-I
feat(lib): implement memcpy_s in lib
To support memcpy_s for better security purpose
to avoid overflowing the dest while copy from src.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I63c3ea6a3e99c10d69be6bce04843c14b0a28a4d
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| f4d011b0 | 12-Jun-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "psci-osi" into integration
* changes:
fix(psci): add optional pwr_domain_validate_suspend to plat_psci_ops_t
fix(sc7280): update pwr_domain_suspend
fix(fvp): update p
Merge changes from topic "psci-osi" into integration
* changes:
fix(psci): add optional pwr_domain_validate_suspend to plat_psci_ops_t
fix(sc7280): update pwr_domain_suspend
fix(fvp): update pwr_domain_suspend
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| 1c0612d8 | 09-Jun-2023 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "chore: remove unused and undefined function" into integration |
| c64681d0 | 08-Jun-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "feat(aarch64): add stack debug information to assembly routines" into integration |
| 6e1ae307 | 07-Jun-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(qemu): fix 32-bit builds with stack protector" into integration |
| 01c1b3e1 | 25-Feb-2023 |
Raghu Krishnamurthy <raghu.ncstate@gmail.com> |
chore: remove unused and undefined function
Clean up unused function
Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
Change-Id: Ib761d04070f7eb7e0dddad4ad885ce11f82582b8 |
| e1c0a472 | 06-Jun-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "dummy_feat_aa32" into integration
* changes:
feat(cpufeat): deny AArch64-only features when building for AArch32
feat(cpufeat): add AArch32 PAN detection support |
| 1d64109e | 06-Jun-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "st-fixes" into integration
* changes:
fix(spi-nand): add Quad Enable management
fix(st-clock): disabling CKPER clock is not functional on stm32mp13
fix(st-uart): skip
Merge changes from topic "st-fixes" into integration
* changes:
fix(spi-nand): add Quad Enable management
fix(st-clock): disabling CKPER clock is not functional on stm32mp13
fix(st-uart): skip console flush if UART is disabled
fix(st): flush UART at the end of uart_read()
fix(stm32mp1): use the BSEC nodes compatible for stm32mp13
fix(stm32mp13-fdts): correct the BSEC nodes compatible
fix(stm32mp1-fdts): move /omit-if-no-ref/ to overlay files
fix(stm32mp1): properly check PSCI functions return
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| a0f3b552 | 05-Jun-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "chore: rename Makalu to Cortex-A715" into integration |
| f8328853 | 10-Mar-2023 |
Boyan Karatotev <boyan.karatotev@arm.com> |
feat(aarch64): add stack debug information to assembly routines
Debugging assembly is painful as it is, and having no useful stack trace
does not help. Code must emit CFI directives whenever the sta
feat(aarch64): add stack debug information to assembly routines
Debugging assembly is painful as it is, and having no useful stack trace
does not help. Code must emit CFI directives whenever the stack moves to
enable stack traces. Otherwise, the layout of the stack frame is
ambiguous, the debugger gives up, and shows nothing. The compiler does
this automatically for C but not assembly.
Add this information to the (currently unused) func_prologue macro.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ief5fd672285df8d9d90fa6a2214b5c6e45eddd81
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| 9027be6f | 05-Jun-2023 |
Soby Mathew <soby.mathew@arm.com> |
Merge "feat(xlat): detect 4KB and 16KB page support when FEAT_LPA2 is present" into integration |
| bff074dd | 03-May-2023 |
Javier Almansa Sobrino <javier.almansasobrino@arm.com> |
feat(xlat): detect 4KB and 16KB page support when FEAT_LPA2 is present
At the moment, TF-A does not need to access VAs or PAs larger than
48 bits, so this patch just enables proper detection of supp
feat(xlat): detect 4KB and 16KB page support when FEAT_LPA2 is present
At the moment, TF-A does not need to access VAs or PAs larger than
48 bits, so this patch just enables proper detection of support
for 4KB and 16KB granularity with 52 bits address support.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: Iccebbd5acc21f09dbb234ef21a802300e290ec18
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| 7f126ccf | 05-Jun-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "cot_cca_nvctr" into integration
* changes:
feat(fvp): mock support for CCA NV ctr
feat(auth): add CCA NV ctr to CCA CoT
feat(build): pass CCA NV ctr option to cert_cr
Merge changes from topic "cot_cca_nvctr" into integration
* changes:
feat(fvp): mock support for CCA NV ctr
feat(auth): add CCA NV ctr to CCA CoT
feat(build): pass CCA NV ctr option to cert_create
feat(cert-create): add new option for CCA NV ctr
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| 463655cc | 02-Jun-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "fix(measured-boot): don't strip last non-0 char" into integration |
| d3488614 | 04-May-2023 |
Wing Li <wingers@google.com> |
fix(psci): add optional pwr_domain_validate_suspend to plat_psci_ops_t
This patch adds a new optional member `pwr_domain_validate_suspend` to
the `plat_psci_ops_t` structure that allows a platform t
fix(psci): add optional pwr_domain_validate_suspend to plat_psci_ops_t
This patch adds a new optional member `pwr_domain_validate_suspend` to
the `plat_psci_ops_t` structure that allows a platform to optionally
perform platform specific validations in OS-initiated mode. This is
conditionally compiled into the build depending on the value of the
`PSCI_OS_INIT_MODE` build option.
In https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/17682,
the return type of the `pwr_domain_suspend` handler was updated from
`void` to `int` to allow a platform to optionally perform platform
specific validations in OS-initiated mode. However, when an error code
other than `PSCI_E_SUCCESS` is returned, the current exit path does not
undo the operations in `psci_suspend_to_pwrdown_start`, and as a result,
the system ends up in an unexpected state.
The fix in this patch prevents the need to undo the operations in
`psci_suspend_to_pwrdown_start`, by allowing the platform to first
perform any necessary platform specific validations before the PSCI
generic code proceeds to the point of no return where the CPU_SUSPEND
request is expected to complete successfully.
Change-Id: I05d92c7ea3f5364da09af630d44d78252185db20
Signed-off-by: Wing Li <wingers@google.com>
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