chore: rename hermes to neoverse-n3

Rename hermes cpu to Neoverse-N3

Change-Id: I912d4c824c5004a8c1909c68fef77f1f5e202b8a
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

feat(cpus): support to update External LLC presence in Neoverse V2

The CPUECTLR_EL1.EXTLLC bit indicates that an external last level
cache(LLC) is present in the system. The default value is interna

feat(cpus): support to update External LLC presence in Neoverse V2

The CPUECTLR_EL1.EXTLLC bit indicates that an external last level
cache(LLC) is present in the system. The default value is internal LLC.
Some systems which may have External LLC can enable the External LLC
presece with new build option 'NEOVERSE_Vx_EXTERNAL_LLC'.

Change-Id: I740947f1ef78e31626dc5b96f6d6dc6658d0120f
Signed-off-by: Younghyun Park <younghyunpark@google.com>

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feat((smccc): add version FID for PMF

Introduce a version FID for PMF.

Change-Id: I6b0a7f54aefc2839704e03c5da2243d7c85f8a49
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

refactor(smccc): move pmf to vendor el3 calls

Move pmf support to vendor-specific EL3 Monitor Service Calls. Remove
pmf call count as it's not supported in vendor-specific el3 as per
SMCCC Documenta

refactor(smccc): move pmf to vendor el3 calls

Move pmf support to vendor-specific EL3 Monitor Service Calls. Remove
pmf call count as it's not supported in vendor-specific el3 as per
SMCCC Documentation 1.5:
https://developer.arm.com/documentation/den0028/latest

Add a deprecation notice to inform PMF is moved from arm-sip range to
vendor-specific EL3 range. PMF support from arm-sip range will be
removed and will not available after TF-A 2.12 release.

Change-Id: Ie1e14aa601d4fc3db352cd5621d842017a18e9ec
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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refactor(smccc): move debugfs to vendor el3 calls

Move debugfs to Vendor-Specific EL3 Monitor Service Calls.
Function Identifier for Vendor-Specific EL3 Monitor Service is '7' and
allocated subrange

refactor(smccc): move debugfs to vendor el3 calls

Move debugfs to Vendor-Specific EL3 Monitor Service Calls.
Function Identifier for Vendor-Specific EL3 Monitor Service is '7' and
allocated subranges of Function identifiers to different services are:

0x87000000-0x8700FFFF-SMC32: Vendor-Specific EL3 Monitor Service Calls
0xC7000000-0xC700FFFF-SMC64: Vendor-Specific EL3 Monitor Service Calls

Amend Debugfs FID's to use this range and id.

Add a deprecation notice to inform debugfs moved from arm-sip range to
Vendor-Specific EL3 range. Debugfs support from arm-sip range will be
removed and will not be available after TF-A 2.12 release.

Reference to debugfs component level documentation:
https://trustedfirmware-a.readthedocs.io/en/latest/components/debugfs-design.html#overview

Change-Id: I97a50170178f361f70c95ed0049bc4e278de59d7
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(smccc): add vendor specific el3 id

Add vendor specific el3 function id and update docs for the same.

SMCCC Documentation reference:
https://developer.arm.com/documentation/den0028/latest

Chan

feat(smccc): add vendor specific el3 id

Add vendor specific el3 function id and update docs for the same.

SMCCC Documentation reference:
https://developer.arm.com/documentation/den0028/latest

Change-Id: Ieeb63608ad74d7b764d7131d8a92ecf10053c50d
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes from topic "rss_rse_rename" into integration

* changes:
refactor(changelog): change all occurrences of RSS to RSE
refactor(qemu): change all occurrences of RSS to RSE
refactor(fv

Merge changes from topic "rss_rse_rename" into integration

* changes:
refactor(changelog): change all occurrences of RSS to RSE
refactor(qemu): change all occurrences of RSS to RSE
refactor(fvp): change all occurrences of RSS to RSE
refactor(fiptool): change all occurrences of RSS to RSE
refactor(psa): change all occurrences of RSS to RSE
refactor(fvp): remove leftovers from rss measured boot support
refactor(tc): change all occurrences of RSS to RSE
docs: change all occurrences of RSS to RSE
refactor(measured-boot): change all occurrences of RSS to RSE
refactor(rse): change all occurrences of RSS to RSE
refactor(psa): rename all 'rss' files to 'rse'
refactor(tc): rename all 'rss' files to 'rse'
docs: rename all 'rss' files to 'rse'
refactor(measured-boot): rename all 'rss' files to 'rse'
refactor(rss): rename all 'rss' files to 'rse'

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Merge changes from topic "hm/handoff" into integration

* changes:
feat(handoff): add support for RESET_TO_BL2
feat(arm): support FW handoff b/w BL1 & BL2
feat(handoff): add TL source files to

Merge changes from topic "hm/handoff" into integration

* changes:
feat(handoff): add support for RESET_TO_BL2
feat(arm): support FW handoff b/w BL1 & BL2
feat(handoff): add TL source files to BL1
feat(handoff): add TE's for BL1 handoff interface
refactor(bl1): clean up bl2 layout calculation
feat(arm): support FW handoff b/w BL2 & BL31

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feat(handoff): add TE's for BL1 handoff interface

`TL_TAG_RW_MEM_LAYOUT64` encapsulates a structure used to represent the
layout of a region of memory on 64-bit platforms [2]. In TF-A this is
used t

feat(handoff): add TE's for BL1 handoff interface

`TL_TAG_RW_MEM_LAYOUT64` encapsulates a structure used to represent the
layout of a region of memory on 64-bit platforms [2]. In TF-A this is
used to represent the `meminfo_t` structure passed between BL1 and BL2,
which provides BL2 with information about the space it has available in
BL2. The `TL_TAG_TB_FW_CONFIG` entry type encapsulates the trusted
bootloader firmware configuration [1].

[1] https://github.com/FirmwareHandoff/firmware_handoff/pull/37
[2] https://github.com/FirmwareHandoff/firmware_handoff/pull/36

Change-Id: I1e0eeec2ec204e469896490d42a9dce9b1b2f209
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(cpus): workaround for Cortex-X4 erratum 2763018

Cortex-X4 erratum 2763018 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2.

The workaround is to set bit[47] of CP

fix(cpus): workaround for Cortex-X4 erratum 2763018

Cortex-X4 erratum 2763018 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2.

The workaround is to set bit[47] of CPUACTLR3_EL1 register.
Setting this chicken bit might have a small impact on power
and negligible impact on performance.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2432808/latest

Change-Id: Ia188e08c2eb2952923ec72e2a56efdeea836fe1e
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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refactor(psa): change all occurrences of RSS to RSE

Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id

refactor(psa): change all occurrences of RSS to RSE

Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I606e2663fb3719edf6372d6ffa4f1982eef45994

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refactor(psa): rename all 'rss' files to 'rse'

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I379c471c541dda25d8ee9087fcf67e05b4204474

fix(cm): add more feature registers to EL1 context mgmt

The following system registers are made part of save and restore
operations for EL1 context:

TRFCR_EL1
SCXTNUM_EL0
SCXTNUM_EL1
GCSCR_EL1
GCSC

fix(cm): add more feature registers to EL1 context mgmt

The following system registers are made part of save and restore
operations for EL1 context:

TRFCR_EL1
SCXTNUM_EL0
SCXTNUM_EL1
GCSCR_EL1
GCSCRE0_EL1
GCSPR_EL1
GCSPR_EL0

Change-Id: I1077112bdc29a6c9cd39b9707d6cf10b95fa15e3
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge changes Ic40e1b7a,I0398b550,Ife594ed6,I3eb0f29b into integration

* changes:
fix(gpt): unify logging messages
chore(gpt): remove gpt_ prefix
feat(aarch64): add functions for TLBI RPALOS

Merge changes Ic40e1b7a,I0398b550,Ife594ed6,I3eb0f29b into integration

* changes:
fix(gpt): unify logging messages
chore(gpt): remove gpt_ prefix
feat(aarch64): add functions for TLBI RPALOS
feat(locks): add bitlock

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Merge changes from topic "lto-fixes" into integration

* changes:
fix(bl1): add missing `__RW_{START,END}__` symbols
fix(fvp): don't check MPIDRs with the power controller in BL1
fix(arm): only

Merge changes from topic "lto-fixes" into integration

* changes:
fix(bl1): add missing `__RW_{START,END}__` symbols
fix(fvp): don't check MPIDRs with the power controller in BL1
fix(arm): only expose `arm_bl2_dyn_cfg_init` to BL2
fix(cm): hide `cm_init_context_by_index` from BL1
fix(bl1): add missing spinlock dependency

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feat(locks): add bitlock

This patch adds 'bitlock_t' type and bit_lock() and
bit_unlock() to support locking/release functionality
based on individual bit position. These functions use
atomic bit se

feat(locks): add bitlock

This patch adds 'bitlock_t' type and bit_lock() and
bit_unlock() to support locking/release functionality
based on individual bit position. These functions use
atomic bit set and clear instructions which require
FEAT_LSE mandatory from Armv8.1.

Change-Id: I3eb0f29bbccefe6c0f69061aa701187a6364df0c
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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Merge "fix(handoff): correct representation of tag_id" into integration

fix(cm): remove ENABLE_FEAT_MTE usage

commit@c282384dbb45b6185b4aba14efebbad110d18e49
removed ENABLE_FEAT_MTE but missed its usage in
context structure declaration path.

All mte regs that are curre

fix(cm): remove ENABLE_FEAT_MTE usage

commit@c282384dbb45b6185b4aba14efebbad110d18e49
removed ENABLE_FEAT_MTE but missed its usage in
context structure declaration path.

All mte regs that are currently context saved/restored
are needed only when FEAT_MTE2 is enabled, so move to
usage of FEAT_MTE2 and remove FEAT_MTE usage

Change-Id: I6b4417485fa6b7f52a31045562600945e48e81b7
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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fix(cm): hide `cm_init_context_by_index` from BL1

BL1 requires the context management library but does not use or
implement `cm_init_context_by_index`. This change ensures that is not
compiled into

fix(cm): hide `cm_init_context_by_index` from BL1

BL1 requires the context management library but does not use or
implement `cm_init_context_by_index`. This change ensures that is not
compiled into BL1, as linking with LTO enabled causes an undefined
reference for this function.

Change-Id: I4a4602843bd75bc4f47b3e0c4c5a6efce1514ef6
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(cm): add more system registers to EL1 context mgmt

The following system registers are made part of save and restore
operations for EL1 context:
MDCCINT_EL1
MDSCR_EL1
DISR_EL1
PIRE0_EL1

fix(cm): add more system registers to EL1 context mgmt

The following system registers are made part of save and restore
operations for EL1 context:
MDCCINT_EL1
MDSCR_EL1
DISR_EL1
PIRE0_EL1
PIR_EL1
POR_EL1
S2POR_EL1
TCR2_EL1

Some of these registers are available as part of core Armv8-A
architecture while others are made available through various
architectural extensions.

Change-Id: I507dccb9053ba177e1b98100fceccd1f32bdfc5c
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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fix(handoff): correct representation of tag_id

The tag ID is a 3-byte field used to identify the contents of a TE. In
our library, the internal representation of the tag is a 2 byte field.
We curren

fix(handoff): correct representation of tag_id

The tag ID is a 3-byte field used to identify the contents of a TE. In
our library, the internal representation of the tag is a 2 byte field.
We currently ignore the top byte of this field, marking it res0. This
causes problems when dealing with non-standard TE types, whose range
starts at 0xff_f000. This commit fixes this by using a bit-field with a
24-bit width, and packing `transfer_list_entry`.

Change-Id: Ib3c212f964b64f528ad6f3dd6ab8b4597b877cd9
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(handoff): add additional TE tags

`TL_TAG_EXEC_EP_INFO64` type entries represent the `entry_point_info_t`
data structure. This structure provides the consumer with the execution
environment of a

feat(handoff): add additional TE tags

`TL_TAG_EXEC_EP_INFO64` type entries represent the `entry_point_info_t`
data structure. This structure provides the consumer with the execution
environment of an image. This is needed primarily in BL31 to execute
subsequent images i.e. BL32, BL33, or NT FW.

`TL_TAG_DT_SPMC_MANIFEST` holds the SPMC (Secure Partition Manager Core)
manifest image which is in DT format.

Change-Id: I80c4a72d639851457bc3c9b158b2e56041e8b29a
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge changes from topic "mte_fixes" into integration

* changes:
build(changelog): move mte to mte2
refactor(mte): remove mte, mte_perm

refactor(mte): remove mte, mte_perm

Currently both FEAT_MTE and FEAT_MTE_PERM aren't used for enabling
of any feature bits in EL3. So remove both FEAT handling.

All mte regs that are currently cont

refactor(mte): remove mte, mte_perm

Currently both FEAT_MTE and FEAT_MTE_PERM aren't used for enabling
of any feature bits in EL3. So remove both FEAT handling.

All mte regs that are currently context saved/restored are needed
only when FEAT_MTE2 is enabled, so move to usage of FEAT_MTE2 and
remove FEAT_MTE usage.

BREAKING CHANGE: Any platform or downstream code trying to use
SCR_EL3.ATA bit(26) will see failures as this is now moved to be
used only with FEAT_MTE2 with
commit@ef0d0e5478a3f19cbe70a378b9b184036db38fe2

Change-Id: Id01e154156571f7792135639e17dc5c8d0e17cf8
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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chore: rename Poseidon to Neoverse V3

Rename Neoverse Poseidon to Neoverse V3, make changes
to related build flags, macros, file names etc.

Change-Id: I9e40ba8f80b7390703d543787e6cd2ab6301e891
Sign

chore: rename Poseidon to Neoverse V3

Rename Neoverse Poseidon to Neoverse V3, make changes
to related build flags, macros, file names etc.

Change-Id: I9e40ba8f80b7390703d543787e6cd2ab6301e891
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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