Merge "chore: update to use Arm word across TF-A" into integration

chore: update to use Arm word across TF-A

Align entire TF-A to use Arm in copyright header.

Change-Id: Ief9992169efdab61d0da6bd8c5180de7a4bc2244
Signed-off-by: Govindraj Raja <govindraj.raja@arm.co

chore: update to use Arm word across TF-A

Align entire TF-A to use Arm in copyright header.

Change-Id: Ief9992169efdab61d0da6bd8c5180de7a4bc2244
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes Ic1796898,I93bd392a into integration

* changes:
fix(errata): workaround for Cortex A78 AE erratum 2395408
fix(errata): workaround for Cortex A78 AE erratum 2376748

fix(errata): workaround for Cortex A78 AE erratum 2395408

Cortex A78 AE erratum 2395408 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.

This erratum states, "A translation t

fix(errata): workaround for Cortex A78 AE erratum 2395408

Cortex A78 AE erratum 2395408 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.

This erratum states, "A translation table walk that matches an
existing L1 prefetch with a read request outstanding on CHI might
fold into the prefetch, which might lead to data corruption for
a future instruction fetch"

This erratum is avoided by setting CPUACTLR2_EL1[40] to 1 to
disable folding of demand requests into older prefetches with
L2 miss requests outstanding.

SDEN is available at https://developer.arm.com/documentation/SDEN-1707912

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ic17968987ca3c67fa7f64211bcde6dfcb35ed5d6

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fix(errata): workaround for Cortex A78 AE erratum 2376748

Cortex A78 AE erratum 2376748 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.

The erratum states, "A PE executing a

fix(errata): workaround for Cortex A78 AE erratum 2376748

Cortex A78 AE erratum 2376748 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.

The erratum states, "A PE executing a PLDW or PRFM PST instruction
that lies on a mispredicted branch path might cause a second PE
executing a store exclusive to the same cache line address to fail
continuously."

The erratum is avoided by setting CPUACTLR2_EL1[0] to 1 to force
PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidations
to other PE caches. There might be a small performance degradation
to this workaround for certain workloads that share data.

SDEN is available at https://developer.arm.com/documentation/SDEN-1707912

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I93bd392a870d4584f3e12c8e4626dbe5a3a40a4d

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Merge "fix(security): workaround for CVE-2022-23960 for A76AE, A78AE, A78C" into integration

fix(security): workaround for CVE-2022-23960 for A76AE, A78AE, A78C

Implements the loop workaround for Cortex-A76AE, Cortex-A78AE and
Cortex-A78C.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Sig

fix(security): workaround for CVE-2022-23960 for A76AE, A78AE, A78C

Implements the loop workaround for Cortex-A76AE, Cortex-A78AE and
Cortex-A78C.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Change-Id: I5c838f5b9d595ed3c461a7452bd465bd54acc548

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Merge "feat(cpus): workaround for Cortex A78 AE erratum 1941500" into integration

feat(cpus): workaround for Cortex A78 AE erratum 1941500

Cortex A78 AE erratum 1941500 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.

This erratum is avoided by by setting

feat(cpus): workaround for Cortex A78 AE erratum 1941500

Cortex A78 AE erratum 1941500 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.

This erratum is avoided by by setting CPUECTLR_EL1[8] to 1.
There is a small performance cost (<0.5%) for setting this
bit.

SDEN is available at https://developer.arm.com/documentation/SDEN1707912/0900

Change-Id: I2d72666468b146714a0340ba114ccf0f5165b39c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge changes from topics "rename-herculesae-a78ae", "rename-zeus-v1" into integration

* changes:
Rename Neoverse Zeus to Neoverse V1
Rename Cortex Hercules AE to Cortex 78 AE

Rename Cortex Hercules AE to Cortex 78 AE

Change-Id: Ic0ca51a855660509264ff0d084c068e1421ad09a
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>