feat(nxp-clk): add minimal set of S32CC clock ids

The clock IDs are organized into categories, which are determined based
on the first 2 MSB bits for each ID. Currently, there are two big
categories

feat(nxp-clk): add minimal set of S32CC clock ids

The clock IDs are organized into categories, which are determined based
on the first 2 MSB bits for each ID. Currently, there are two big
categories: hardware and software-defined clocks.

The first category refers to clock IDs understood by the S32CC PLL muxes
and MC_CGM module muxes and is immutable. The last category of the
clocks includes software-defined IDs for clocks to allow an easy
representation of the hierarchy.

Change-Id: Idc079feb3ca5f92d8bf337ef09efad006e267088
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(st-clock): add STM32MP2 clock driver

This driver manages the clocks on STM32MP2 platforms.
It uses a dedicated RCC (Reset and Clock Control) peripheral.

Change-Id: I6ba2173e73222269a2dfca4c689

feat(st-clock): add STM32MP2 clock driver

This driver manages the clocks on STM32MP2 platforms.
It uses a dedicated RCC (Reset and Clock Control) peripheral.

Change-Id: I6ba2173e73222269a2dfca4c6897229276a150c0
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>

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feat(st-reset): add system reset management

Add the system reset management into the stm32mp
reset driver.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I748f10de2398e1323160f479

feat(st-reset): add system reset management

Add the system reset management into the stm32mp
reset driver.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I748f10de2398e1323160f479f99e92abd2f65dca

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fix(intel): remove redundant BIT_32 macro

BIT_32 macro is already defined as part of the utils_def.h and included
through mmc.h

Suggested-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I7921681e

fix(intel): remove redundant BIT_32 macro

BIT_32 macro is already defined as part of the utils_def.h and included
through mmc.h

Suggested-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I7921681ee9af7d65e8eab5a0bf1d5236ecfed1a4
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "add_clk_callbacks" into integration

* changes:
feat(clk): add set_rate callback
feat(clk): add set_parent callback

feat(clk): add set_rate callback

This callback will be used to set a clock's rate if the underlying clock
driver supports this option. The function's last parameter is an output
parameter, storing t

feat(clk): add set_rate callback

This callback will be used to set a clock's rate if the underlying clock
driver supports this option. The function's last parameter is an output
parameter, storing the actual frequency set by the clock driver, as it
may not precisely match the requested rate in some cases.

Change-Id: I6a399bf6f64407d5fbff36407561e4bf18104cf1
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge "refactor(dice): save parent context handle" into integration

feat(clk): add set_parent callback

This callback will be used to set a clock's parent if the underlying
clock driver supports this option.

Change-Id: Ie8a77d17dd3cc867bd520217b481cd188317a9c9
Signe

feat(clk): add set_parent callback

This callback will be used to set a clock's parent if the underlying
clock driver supports this option.

Change-Id: Ie8a77d17dd3cc867bd520217b481cd188317a9c9
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge "feat(fvp): add cpu power control" into integration

feat(st-gpio): add set GPIO config API

Add get and set GPIO level from bank and pin value.
Add functions to set a pad in GPIO configuration
and to apply some settings.

Change-Id: I5e3acb5c95cd03f3e

feat(st-gpio): add set GPIO config API

Add get and set GPIO level from bank and pin value.
Add functions to set a pad in GPIO configuration
and to apply some settings.

Change-Id: I5e3acb5c95cd03f3e130e1a263b221b956cb3c8d
Signed-off-by: Pascal Paillet <p.paillet@st.com>

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feat(fvp): add cpu power control

Most newer CPU's have DSU and CPU power control core-off bit which
means before turning off CPUs from base power controller we need to
turn individual cores off from

feat(fvp): add cpu power control

Most newer CPU's have DSU and CPU power control core-off bit which
means before turning off CPUs from base power controller we need to
turn individual cores off from CPU Power control.

However there are certain older CPU's that don't have DSU and
don't support CPUPWRCTRL_EL1, so populate them as a list
and ignore setting core-off bit for those older CPU's as all newer
CPU's have them.

Note: unfortunately there is no mechanism to identify if a DSU is
present and CPUPWRCTRL_EL1 is supported through any CPU control
registers and CPUPWRCTRL_EL1 is supported only for ARM64 platforms
and not available in ARM32 platforms.

Change-Id: Iba6c3c8db60dbeb177cead7ebc65df8265860da7
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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refactor(dice): save parent context handle

Improve the restart handling of DPE. In the case of a restart
scenario where only that core is restarted which executes
the DPE client, but the core execut

refactor(dice): save parent context handle

Improve the restart handling of DPE. In the case of a restart
scenario where only that core is restarted which executes
the DPE client, but the core executes the DPE service
remains up and running. In this case, client needs to save
a valid context handle to be able to send commands again
to the DPE service during the new boot sequence.

BL1 saves a valid parent context handle to SDS
before passing the execution to BL2. This handle
can be used in case of a restart scenario when AP
is restarted but RSE is not. Because in that case
RSE does not save an initial context handle to SDS,
which meant to be used by AP during the boot process.

By then the very first initial context handle is
invalidated because it was already used in the
previous boot cycle by BL1.

BL2 does not need to do this, because the cold
boot starts with BL1.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Id14eefd2ec758f89f672af176e4f5386a397fa35

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refactor(st-clock): remove unused clk function in API

Remove the unused functions in stm32mp clk API:
- stm32mp_stgen_get_counter (change to static, no more exported)
- stm32mp_stgen_restore_counter

refactor(st-clock): remove unused clk function in API

Remove the unused functions in stm32mp clk API:
- stm32mp_stgen_get_counter (change to static, no more exported)
- stm32mp_stgen_restore_counter

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ib6ca72723eac3e133f1ca0dee504ef344c72e0bf

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feat(st-clock): add function to restore generic timer rate

Add a function to restore the CPU generic timer rate from STGEN content.
After wake-up from LPLV-Stop2, STGEN content is not lost, but gene

feat(st-clock): add function to restore generic timer rate

Add a function to restore the CPU generic timer rate from STGEN content.
After wake-up from LPLV-Stop2, STGEN content is not lost, but generic timer
has been reset.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: I6f91dbd051f76383e9ff1d6bb86225d373dbf33a

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refactor(auth): remove HW_CONFIG reference from BL1 CoT file

Remove the 'HW_CONFIG' reference from the BL1 CoT file, as BL1
does not play any role in loading the hw_config image. This
reference was

refactor(auth): remove HW_CONFIG reference from BL1 CoT file

Remove the 'HW_CONFIG' reference from the BL1 CoT file, as BL1
does not play any role in loading the hw_config image. This
reference was incorrectly added to the BL1 CoT file.

Change-Id: I9c1d9abce65844eaa1f41ab4f98d3c258ab7a8d2
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(tc): add MHUv3 doorbell support on TC3

Enables the doorbell channels in MHUv3 for TC3.

Change-Id: Ib4f47df3e54f9182939ea6c1d8bc1a66a3c03094
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.

feat(tc): add MHUv3 doorbell support on TC3

Enables the doorbell channels in MHUv3 for TC3.

Change-Id: Ib4f47df3e54f9182939ea6c1d8bc1a66a3c03094
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge changes from topic "ar/pmuSaveRestore" into integration

* changes:
feat(tc): add save/restore DSU PMU register support
feat(dsu): save/restore DSU PMU register
feat(plat): add platform A

Merge changes from topic "ar/pmuSaveRestore" into integration

* changes:
feat(tc): add save/restore DSU PMU register support
feat(dsu): save/restore DSU PMU register
feat(plat): add platform API that gets cluster ID

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feat(mbedtls): update config for 3.6.0

Further, remove reliance of mbedtls_md_psa_alg_from_type on
the actual values of the PSA_ALG_... defines.

And work around a prior bug that would try to import

feat(mbedtls): update config for 3.6.0

Further, remove reliance of mbedtls_md_psa_alg_from_type on
the actual values of the PSA_ALG_... defines.

And work around a prior bug that would try to import a
SubjectPublicKeyInfo into a PSA key. Instead, we import the
SubjectPublicKey itself.

Change-Id: Ib345b0bd4f2994f366629ed162d18814fd05aa2b
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

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feat(dsu): save/restore DSU PMU register

Adds driver support to preserve DSU PMU register values over a DSU
power cycle. This driver needs to be enabled by the platforms that
support DSU and also ne

feat(dsu): save/restore DSU PMU register

Adds driver support to preserve DSU PMU register values over a DSU
power cycle. This driver needs to be enabled by the platforms that
support DSU and also need it's PMU registers to be preserved

Change-Id: I7fc68a3d7d99ee369379aa5cd114fffc763fc0d2
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>

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Merge changes from topic "add_s32g274ardb2_support" into integration

* changes:
feat(s32g274a): enable BL31 stage
feat(s32g274a): add S32G274ARDB2 board support
feat(nxp-drivers): add Linflex

Merge changes from topic "add_s32g274ardb2_support" into integration

* changes:
feat(s32g274a): enable BL31 stage
feat(s32g274a): add S32G274ARDB2 board support
feat(nxp-drivers): add Linflex driver

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feat(nxp-drivers): add Linflex driver

This is a UART controller found on NXP automotive parts.
For instance: S32V, S32G and S32R.

Change-Id: Iff0dd0c379633ac0651e5db287537c87666b57d2
Signed-off-by:

feat(nxp-drivers): add Linflex driver

This is a UART controller found on NXP automotive parts.
For instance: S32V, S32G and S32R.

Change-Id: Iff0dd0c379633ac0651e5db287537c87666b57d2
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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refactor(measured-boot): change all occurrences of RSS to RSE

Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".

Signed-off-by: Tamas Ban <tamas.ban@arm.com>

refactor(measured-boot): change all occurrences of RSS to RSE

Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I8c2fcbdf1de1c75f9969d28bc15e0b3500071404

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refactor(rse): change all occurrences of RSS to RSE

Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id

refactor(rse): change all occurrences of RSS to RSE

Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I9f72ad36ec233d7eaac3ce9e2f2b010130e1fa94

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refactor(measured-boot): rename all 'rss' files to 'rse'

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I3bd987456ad0f5c7a003960dd543efad2ce668a8

refactor(rss): rename all 'rss' files to 'rse'

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I6cfca1d67e246d5079f683241021ed039cc27f74