chore(mbedtls): remove hash configs

After the upgrade to mbedtls 3.6.0, some of these configuation limitations
are no longer present.

Size chages:
build config | executable | Delta
-------------|--

chore(mbedtls): remove hash configs

After the upgrade to mbedtls 3.6.0, some of these configuation limitations
are no longer present.

Size chages:
build config | executable | Delta
-------------|------------|-------
tbb ecdsa | bl1 | -176
-------------|------------|-------
tbb rsa | bl1 | -192
| bl2 | -4096
-------------|------------|-------
drtm | romlib | -576
-------------|------------|-------
spm | romlib | -576
-------------|------------|-------
mb384 | romlib | -1016

Change-Id: I019bc59adc93cf95f6f28ace9579e7bf1e785b62
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

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Merge changes from topic "stm32mp2_bl2_updates" into integration

* changes:
feat(stm32mp2): load fw-config file
feat(stm32mp2): add fw-config compilation
feat(stm32mp2-fdts): add fw-config fil

Merge changes from topic "stm32mp2_bl2_updates" into integration

* changes:
feat(stm32mp2): load fw-config file
feat(stm32mp2): add fw-config compilation
feat(stm32mp2-fdts): add fw-config files for STM32MP257F-EV1
feat(stm32mp2-fdts): add fw-config file
feat(stm32mp2-fdts): add clock tree for STM32MP257F-EV1
feat(stm32mp2): enable DDR sub-system clock
feat(stm32mp2): add fixed regulators support
feat(stm32mp2): print board info
feat(stm32mp2): display CPU info
feat(stm32mp2): get chip ID
feat(stm32mp2): add BL2 boot first steps
feat(stm32mp2): add defines for the PWR peripheral
feat(stm32mp2-fdts): add SD-card and eMMC support on STM32MP257F-EV1
feat(stm32mp2-fdts): add sdmmc pins definition
feat(stm32mp2-fdts): add sdmmc nodes in SoC DT file
feat(stm32mp2-fdts): add io_policies
feat(stm32mp2-fdts): remove pins-are-numbered

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feat(nxp-clk): enable UART clock

Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz

feat(nxp-clk): enable UART clock

Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz by changing the clock source from FIRC to
PERIPH PLL PHI3.

Change-Id: I3160dc6860ebf441c9bea8eaf9d8d12de48bd647
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add PERIPH PLL enablement

Peripheral PLL is one of the platform's PLLs, providing a clock for
peripherals such as UART, QSPI, uSDHC, SPI and CAN. Its source can be
either the FIRC or

feat(nxp-clk): add PERIPH PLL enablement

Peripheral PLL is one of the platform's PLLs, providing a clock for
peripherals such as UART, QSPI, uSDHC, SPI and CAN. Its source can be
either the FIRC or FXOSC oscillators. It has eight outputs (PHIs) and
their frequencies can be controlled programmatically using output
dividers. An additional output clocks the PERIPH DFS using the VCO
frequency of the PERIPH PLL.

Change-Id: I637294b2da94f35e95dc1750dad36c129a276bb9
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(stm32mp2): enable DDR sub-system clock

Create a DDR helper files, and add a function to enable DDR clocks
in RCC_DDRCPCFGR register.
Call this ddr_sub_system_clk_init() just before clock driver

feat(stm32mp2): enable DDR sub-system clock

Create a DDR helper files, and add a function to enable DDR clocks
in RCC_DDRCPCFGR register.
Call this ddr_sub_system_clk_init() just before clock driver init,
as it needs to be done before enabling DDR PLL clock (PLL2).

Change-Id: I365d6aa034363d0c036ce2d9f944f077ba86e193
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp2): add defines for the PWR peripheral

This peripheral controls power on STM232MP2 platform.

Change-Id: Ieedca580b5ec897a2fac9e88c7c8c327df6f19c2
Signed-off-by: Yann Gautier <yann.gauti

feat(stm32mp2): add defines for the PWR peripheral

This peripheral controls power on STM232MP2 platform.

Change-Id: Ieedca580b5ec897a2fac9e88c7c8c327df6f19c2
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge changes from topic "nxp-s32g2/add-xbar-clk" into integration

* changes:
feat(nxp-clk): enable the XBAR clock
feat(nxp-clk): add dependencies for the XBAR clock
feat(nxp-clk): add CGM0 in

Merge changes from topic "nxp-s32g2/add-xbar-clk" into integration

* changes:
feat(nxp-clk): enable the XBAR clock
feat(nxp-clk): add dependencies for the XBAR clock
feat(nxp-clk): add CGM0 instance
feat(nxp-clk): add DFS module enablement
feat(nxp-clk): add clock objects for ARM DFS
refactor(nxp-clk): organize early clocks in groups

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feat(nxp-clk): add dependencies for the XBAR clock

Add all clock modules required to enable the XBAR clock, including the
DFS, its output dividers and MC_CGM muxes.

Change-Id: Ib9cf82c0e40b76863637

feat(nxp-clk): add dependencies for the XBAR clock

Add all clock modules required to enable the XBAR clock, including the
DFS, its output dividers and MC_CGM muxes.

Change-Id: Ib9cf82c0e40b76863637ed7602c3a09411d17615
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add CGM0 instance

Introduce the MC_CGM0 instance responsible for XBAR and other peripheral
clocks.

Change-Id: Icf1e9ce6e71e4ff446835d1e7b6522bfb6f2b4b6
Signed-off-by: Ghennadi Procop

feat(nxp-clk): add CGM0 instance

Introduce the MC_CGM0 instance responsible for XBAR and other peripheral
clocks.

Change-Id: Icf1e9ce6e71e4ff446835d1e7b6522bfb6f2b4b6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add clock objects for ARM DFS

The DFS modules are connected to the PLL VCO and provide a clock
downstream through a set of output dividers, the frequency of which can
be adjusted prog

feat(nxp-clk): add clock objects for ARM DFS

The DFS modules are connected to the PLL VCO and provide a clock
downstream through a set of output dividers, the frequency of which can
be adjusted programmatically.

Change-Id: Ie945d10fd39e6e40e6c051ccde8486dcfb5bd53f
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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fix(gicv3): incorrect impdef power down sequence

The GICR_WAKER.Sleep and GICR_WAKE.Quiescent functionality is solely
about flushing out the LPI cache and ensuring that the contents are
consistent w

fix(gicv3): incorrect impdef power down sequence

The GICR_WAKER.Sleep and GICR_WAKE.Quiescent functionality is solely
about flushing out the LPI cache and ensuring that the contents are
consistent with external memory.

Hence, as shown in GIC-700 TRM version r3p0, software must poll for
Quiescent bit only if LPIs are supported.

Change-Id: I7d69b208428e24d8a3ff30e81bd1a8ee3d0bda6e
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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feat(nxp-clk): set rate for clock fixed divider

Add set rate support for fixed divider clock modules of whose role is to
reduce the source frequency by a factor.

Change-Id: I8a29a2c5b1a829db0c39640

feat(nxp-clk): set rate for clock fixed divider

Add set rate support for fixed divider clock modules of whose role is to
reduce the source frequency by a factor.

Change-Id: I8a29a2c5b1a829db0c396407c3517c9e66caaa93
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add A53 clock objects

These objects are needed to allow early enablement of the A53 core
clock.

Change-Id: I44d81975c8eba8cc6cfd18aeb6c9b324edaa3f01
Signed-off-by: Ghennadi Procopciu

feat(nxp-clk): add A53 clock objects

These objects are needed to allow early enablement of the A53 core
clock.

Change-Id: I44d81975c8eba8cc6cfd18aeb6c9b324edaa3f01
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): set rate for PLL divider objects

Add implementation for ARM PLL divider rate set mechanism.

Change-Id: I78f4418bcbb5ea0a6ef64675e44bd074d2230ea3
Signed-off-by: Ghennadi Procopciuc <g

feat(nxp-clk): set rate for PLL divider objects

Add implementation for ARM PLL divider rate set mechanism.

Change-Id: I78f4418bcbb5ea0a6ef64675e44bd074d2230ea3
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): set rate for PLL objects

Add implementation for ARM PLL rate set mechanism.

Change-Id: Ic859567bd67747f173d425158cdc581801f7446c
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopci

feat(nxp-clk): set rate for PLL objects

Add implementation for ARM PLL rate set mechanism.

Change-Id: Ic859567bd67747f173d425158cdc581801f7446c
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "add_s32cc_pll" into integration

* changes:
feat(nxp-clk): set parent for ARM PLL and MC_CGM muxes
feat(nxp-clk): add MC_CGM clock objects
feat(nxp-clk): add set_paren

Merge changes from topic "add_s32cc_pll" into integration

* changes:
feat(nxp-clk): set parent for ARM PLL and MC_CGM muxes
feat(nxp-clk): add MC_CGM clock objects
feat(nxp-clk): add set_parent callback
feat(nxp-clk): add clock objects for ARM PLL
feat(nxp-clk): add FXOSC clock enablement

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Merge changes from topic "st_mp2_clk_reset" into integration

* changes:
feat(st-reset): add stm32mp2_reset driver
feat(st-clock): add STM32MP2 clock driver
fix(dt-bindings): update STM32MP2 cl

Merge changes from topic "st_mp2_clk_reset" into integration

* changes:
feat(st-reset): add stm32mp2_reset driver
feat(st-clock): add STM32MP2 clock driver
fix(dt-bindings): update STM32MP2 clock and reset bindings
feat(st-reset): add system reset management

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feat(nxp-clk): add MC_CGM clock objects

The MC_CGM1 clock objects will participate in A53 clocking.

Change-Id: I7309b630d72ac0ad66df7c299b678454220e0581
Signed-off-by: Ghennadi Procopciuc <ghennadi

feat(nxp-clk): add MC_CGM clock objects

The MC_CGM1 clock objects will participate in A53 clocking.

Change-Id: I7309b630d72ac0ad66df7c299b678454220e0581
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add set_parent callback

On S32CC SoCs, the set_parent operation will be used on clock modules
that are mux instances in order to establish the clock source. This will
be used for PLLs

feat(nxp-clk): add set_parent callback

On S32CC SoCs, the set_parent operation will be used on clock modules
that are mux instances in order to establish the clock source. This will
be used for PLLs and MC_CGM muxes.

Change-Id: I7228d379500ea790459b858da8fc0bdcbed4fd62
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add clock objects for ARM PLL

Add all the clock objects needed to describe the ARM PLL, which can be
powered by either FXOSC or FIRC oscillators.

Change-Id: I2585ed38178ca1d5c5485adb

feat(nxp-clk): add clock objects for ARM PLL

Add all the clock objects needed to describe the ARM PLL, which can be
powered by either FXOSC or FIRC oscillators.

Change-Id: I2585ed38178ca1d5c5485adb38af1b3b8d94f1f6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "add_s32cc_fxosc_clk" into integration

* changes:
feat(s32g274a): enable BL2 early clocks
feat(nxp-clk): implement set_rate for oscillators
feat(nxp-clk): add oscillat

Merge changes from topic "add_s32cc_fxosc_clk" into integration

* changes:
feat(s32g274a): enable BL2 early clocks
feat(nxp-clk): implement set_rate for oscillators
feat(nxp-clk): add oscillator clock objects
feat(nxp-clk): add minimal set of S32CC clock ids

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feat(tc): provide target_locality info of AP FW components

The target_locality attribute is meant to specify that
a certain SW component is expected to run and thereby
send DPE commands from a given

feat(tc): provide target_locality info of AP FW components

The target_locality attribute is meant to specify that
a certain SW component is expected to run and thereby
send DPE commands from a given security domain. The DPE
service must be capable of determining the locality of
a client on his own. RSE determines the client's locality
based on the MHU channel used for communication.

If the expected locality (specified by the parent component)
is not matching with the determined locality by DPE
service then command fails.

The goal is to protect against spoofing when a
context_handle is stolen and used by a component
that should not have access.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I96d255de231611cfed10eef4335a47b91c2c94de

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feat(s32g274a): enable BL2 early clocks

s32cc_init_early_clks will be used to increase the frequency of the
clocks which have a performance impact on BL2 boot. This set includes
A53, XBAR, DDR and L

feat(s32g274a): enable BL2 early clocks

s32cc_init_early_clks will be used to increase the frequency of the
clocks which have a performance impact on BL2 boot. This set includes
A53, XBAR, DDR and Linflex clocks. For now, it will only contain the
frequency set for FXOSC. More clock management will be added in the next
commits.

Change-Id: Ie85465884de02f5082185f91749f190f40249c2e
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): implement set_rate for oscillators

The set_rate callback will now be applied to FIRC, FXOSC, and SIRC
oscillators. It is a prerequisite for the upcoming commits that will
utilize this

feat(nxp-clk): implement set_rate for oscillators

The set_rate callback will now be applied to FIRC, FXOSC, and SIRC
oscillators. It is a prerequisite for the upcoming commits that will
utilize this capability.

Change-Id: I82d1545c63b3e15497c1c002ff9ec0d7bf990aa0
Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add oscillator clock objects

The oscillator clock objects will be used to describe the FIRC, FXOSC,
and SIRC clocks, all of which are oscillators on S32CC SoCs.

Change-Id: Icf235cc9b

feat(nxp-clk): add oscillator clock objects

The oscillator clock objects will be used to describe the FIRC, FXOSC,
and SIRC clocks, all of which are oscillators on S32CC SoCs.

Change-Id: Icf235cc9b8f1d95d2c0051ce9a7655fd120289b8
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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