Merge changes from topic "xl/cortex_a510-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A510 erratum 2002389
fix(cpus): workaround for Cortex-A510 erratum 1976290
fix(cpu

Merge changes from topic "xl/cortex_a510-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A510 erratum 2002389
fix(cpus): workaround for Cortex-A510 erratum 1976290
fix(cpus): workaround for Cortex-A510 erratum 2028010
fix(cpus): workaround for Cortex-A510 erratum 2027318
fix(cpus): workaround for Cortex-A510 erratum 1975068
fix(cpus): workaround for Cortex-A510 erratum 1966377
fix(cpus): workaround for Cortex-A510 erratum 1952872
fix(cpus): workaround for Cortex-A510 erratum 1942494
fix(cpus): workaround for Cortex-A510 erratum 1937669
fix(cpus): workaround for Cortex-A510 erratum 1910738

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fix(cpus): workaround for Cortex-A510 erratum 1910738

Cortex-A510 erratum 1910738 is a Cat B erratum that applies to
revision r0p0. It is fixed in r0p1.

This erratum can be avoided by setting IMP_C

fix(cpus): workaround for Cortex-A510 erratum 1910738

Cortex-A510 erratum 1910738 is a Cat B erratum that applies to
revision r0p0. It is fixed in r0p1.

This erratum can be avoided by setting IMP_CPUECTLR_EL1[19] = 1,
IMP_CPUACTLR_EL1[4] = 1 and IMP_CPUACTLR_EL1[26] = 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1873351/latest

Change-Id: I93ebe8dc7908c52239cfe10d063016a58855f17f
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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refactor(cpufeat): unify FEAT_IDTE3's definitions with arch.h

Use the same naming template and put in arch.h to allow for reuse.

Change-Id: I91a28b5f3e75537422d45c2147cb711625f18282
Signed-off-by:

refactor(cpufeat): unify FEAT_IDTE3's definitions with arch.h

Use the same naming template and put in arch.h to allow for reuse.

Change-Id: I91a28b5f3e75537422d45c2147cb711625f18282
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(el3-runtime): generalise sysreg trapping

On a first look, the system register trapping code is quite
straightforward - match the register and call a handler. But looking a
bit more closely,

refactor(el3-runtime): generalise sysreg trapping

On a first look, the system register trapping code is quite
straightforward - match the register and call a handler. But looking a
bit more closely, with the intention of adding a new one, it isn't -
matching is based on opaque magic numbers and handlers have a lot of
duplication.

This patch tries to resolve both of these by hoisting common
functionality up towards common code and using S3 encodings for the
register matching. It also moves things around a bit to make them more
reusable in future.

Change-Id: Ia69289bfb16615312cc7adcc5cc3e319174b1bf0
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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chore(cpufeat): check FEAT_RAS's dependency on FEAT_IESB

Our enablement of FEAT_RAS hinges on the assumption that FEAT_IESB will
also be there. That is true for all cores implemented to date, howeve

chore(cpufeat): check FEAT_RAS's dependency on FEAT_IESB

Our enablement of FEAT_RAS hinges on the assumption that FEAT_IESB will
also be there. That is true for all cores implemented to date, however,
it is not architecturally required. Add a feat detect check to catch
if this assumption ever stops being true.

Change-Id: Ie76f11e1eb76044c68ce18c7ffc39ef9c587d6e0
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(rmmd): replace ENABLE_RME with ENABLE_RMM

RME architectural requirements are now handled under the feature
detection option ENABLE_FEAT_RME. However, the existing ENABLE_RME build
option perfor

feat(rmmd): replace ENABLE_RME with ENABLE_RMM

RME architectural requirements are now handled under the feature
detection option ENABLE_FEAT_RME. However, the existing ENABLE_RME build
option performs RMM-specific tasks such as GPT setup, loading the RMM,
and enabling RMMD support.

Since ENABLE_RME now only controls RMM-related functionality, rename it
to ENABLE_RMM to better reflect its purpose and avoid confusion with
ENABLE_FEAT_RME.

For backward compatibility, setting the legacy ENABLE_RME=1 (until it is
deprecated) will automatically enable both ENABLE_FEAT_RME and
ENABLE_RMM.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Iac945bdffe5002161bf1161b81a5aa7abec68192

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feat(rme): split off ENABLE_FEAT_RME

ENABLE_RME currently controls multiple, distinct aspects of RME support,
including forcing BL2 to EL3, ROOT world page table setup, GPT
initialization, and full

feat(rme): split off ENABLE_FEAT_RME

ENABLE_RME currently controls multiple, distinct aspects of RME support,
including forcing BL2 to EL3, ROOT world page table setup, GPT
initialization, and full RMM loading and handling.

While full CCA support requires all of these steps, some systems running
on FEAT_RME-capable cores do not need or want an RMM. However, such
systems still require TF-A page table entries to set the .NSE bit so
that TF-A accesses are correctly attributed to the ROOT world,
otherwise, enabling the MMU may cause the system to hang.

To address this, a new build option, ENABLE_FEAT_RME, is introduced. It
handles only the .NSE PTE setup and ignores the rest of the RME/RMM
initialization. ENABLE_FEAT_RME follows the ENABLE_FEAT_* convention and
supports values 0–2, with 2 enabling runtime detection.

Full RME functionality remains gated by ENABLE_RME, which now implicitly
enables ENABLE_FEAT_RME, allowing TF-A to run safely on FEAT_RME systems
without requiring an RMM.

Change-Id: I8391652842ff2e62a73b61829c6250c3805d4a4e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "fix(cpufeat): account for FEAT_RME registers in FEAT_FGWTE3" into integration

Merge changes Id23fe0b6,I1d347c12,I4a30850c,I25dcc8ad into integration

* changes:
fix(cm): initialise TCR2_EL2 and HAFGRTR_EL2 for compatibility
refactor(cm): make the REG_INIT_VAL init relation

Merge changes Id23fe0b6,I1d347c12,I4a30850c,I25dcc8ad into integration

* changes:
fix(cm): initialise TCR2_EL2 and HAFGRTR_EL2 for compatibility
refactor(cm): make the REG_INIT_VAL init relationship explicit
feat(cm): propagate EL2 register compatibility init to all worlds
refactor(cm): always call setup_el1_context()

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fix(cpufeat): account for FEAT_RME registers in FEAT_FGWTE3

The FEAT_RME enablement needs to write Granule Protection registers
during boot. So don't include their read-only flags in the initial
FEA

fix(cpufeat): account for FEAT_RME registers in FEAT_FGWTE3

The FEAT_RME enablement needs to write Granule Protection registers
during boot. So don't include their read-only flags in the initial
FEAT_FGWTE3 enablement and leave it for the late one.

Change-Id: I4dd673a462f5bce497a4bdca8fd127a082355a9d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(cpufeat): disable FEAT_RME_GPC3 by default

FEAT_RME_GPC3 was introduced to optimize the L0GPT layout in large
multi-SoC systems.

There is currently no platform use case for this feature, so dis

fix(cpufeat): disable FEAT_RME_GPC3 by default

FEAT_RME_GPC3 was introduced to optimize the L0GPT layout in large
multi-SoC systems.

There is currently no platform use case for this feature, so disable it
by default until required by a platform. Disabling this feature requires:
- GPCCR_EL3.GPCBW = 0 to disable the bypass window
- FGWTE3_EL3.GPCBW_EL3 = 1 to trap accesses to GPCBW_EL3 to EL3

TF-A already disables the bypass window in gpt_enable(). This patch
implements the second requirement by updating FGWTE3_EL3_EARLY_INIT_VAL
to set FGWTE3_EL3.GPCBW_EL3, ensuring that accesses to GPCBW_EL3 trap
to EL3 unless explicitly relaxed later.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I9340307b148f3e54e922bdacefc05dee46e4bacd

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fix(cm): initialise TCR2_EL2 and HAFGRTR_EL2 for compatibility

Older EL2 implementations that do not implement support for these
features but are run on hardware that has them will still experience

fix(cm): initialise TCR2_EL2 and HAFGRTR_EL2 for compatibility

Older EL2 implementations that do not implement support for these
features but are run on hardware that has them will still experience the
effects of these registers. When EL2 is the highest EL in the system,
they reset to safe working values (all 0) but when EL3 is highest it is
EL3's responsibility to do this.

Change-Id: Id23fe0b696b7f434de9522db447222d3f6af1c2d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes I9cf3fd1d,Ia446173b into integration

* changes:
perf(cpufeat): check the lock isn't held before trying to acquire it
refactor(cpufeat): extract exclusive instructions to their own

Merge changes I9cf3fd1d,Ia446173b into integration

* changes:
perf(cpufeat): check the lock isn't held before trying to acquire it
refactor(cpufeat): extract exclusive instructions to their own helpers

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refactor(bl2): data cache invalidate on bl2 entry

Rely on build options BL2_RUNS_AT_EL3 and BL2_INV_DCACHE to invalidate
the data cache upon BL2 entry and this shouldn't be tied with ENABLE_RME
buil

refactor(bl2): data cache invalidate on bl2 entry

Rely on build options BL2_RUNS_AT_EL3 and BL2_INV_DCACHE to invalidate
the data cache upon BL2 entry and this shouldn't be tied with ENABLE_RME
build flag. This also ensures that if a platform sets
BL2_INV_DCACHE, it takes precedence over feature flags.

This change also restores documentation for BL2_INV_DCACHE, which was
accidentally removed by commit 43f35ef51.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I52bdfe351c730f62d79a518327f57b398c7b29c5

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refactor(cpufeat): extract exclusive instructions to their own helpers

Converts code to more proper C, simplifies reading the routine, and
limits how many inline assembly constraints we have to keep

refactor(cpufeat): extract exclusive instructions to their own helpers

Converts code to more proper C, simplifies reading the routine, and
limits how many inline assembly constraints we have to keep track of.

Change-Id: Ia446173bf1cbe2d9bcbd8055cd305c107da4359a
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(lib): remove duplicate macro identifiers

MISRA violation C2012-5.4: Macro identifiers shall be distinct.
Removed the duplicate identifier.

Change-Id: Icd39ae2110b7b201f83433df6d0e1e7107de03e8
S

fix(lib): remove duplicate macro identifiers

MISRA violation C2012-5.4: Macro identifiers shall be distinct.
Removed the duplicate identifier.

Change-Id: Icd39ae2110b7b201f83433df6d0e1e7107de03e8
Signed-off-by: Suraj Kakade <suraj.hanumantkakade@amd.com>

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Merge changes from topic "bk/new_feats" into integration

* changes:
feat(cpufeat): add support for FEAT_HACDBS
feat(cpufeat): add support for FEAT_HDBSS
feat(cpufeat): add support for FEAT_STE

Merge changes from topic "bk/new_feats" into integration

* changes:
feat(cpufeat): add support for FEAT_HACDBS
feat(cpufeat): add support for FEAT_HDBSS
feat(cpufeat): add support for FEAT_STEP2
feat(docs): update the feature guide to mention FEAT_IDTE3
fix(cpufeat): remove the feature list from arch_features.h
docs(cpufeat): add analysis of 2022 features
fix(cpus): use hint instruction instead of the psb mnemonic

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fix(lib): typecast operands to match data type

This corrects the MISRA violation C2012-10.1:
Operands shall not be of an inappropriate essential type.
The condition is explicitly checked against 0U,

fix(lib): typecast operands to match data type

This corrects the MISRA violation C2012-10.1:
Operands shall not be of an inappropriate essential type.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Additionally, the unused macro ZCR_EL2_LEN_MASK has been
removed as it is not referenced anywhere in the codebase.

Change-Id: I854dcbf85295d25db83dafa9dc3bfc88613dbb55
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>
Signed-off-by: Suraj Kakade <suraj.hanumantkakade@amd.com>

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feat(cpufeat): add support for FEAT_HACDBS

The Hardware accelerator for cleaning Dirty state feature also has two
register just like FEAT_HDBSS. They are guarded by a SCR_EL3 bit which
set for NS wo

feat(cpufeat): add support for FEAT_HACDBS

The Hardware accelerator for cleaning Dirty state feature also has two
register just like FEAT_HDBSS. They are guarded by a SCR_EL3 bit which
set for NS world only and are not context switched as a result. There is
no use for this feature at EL3.

Change-Id: Ica7a312d891a1671df8e9f2adbfe464d96bbcd4d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): add support for FEAT_HDBSS

The Hardware Dirty state tracking structure feature has two registers to
enable tracking at lower ELs which are guarded by an SCR_EL3 bit. Set
that bit for

feat(cpufeat): add support for FEAT_HDBSS

The Hardware Dirty state tracking structure feature has two registers to
enable tracking at lower ELs which are guarded by an SCR_EL3 bit. Set
that bit for NS only and do not context switch the registers. There is
no use of the feature at EL3.

Change-Id: I174a256d70a99abfafc65eed3a2fbdaea5ea946d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): add support for FEAT_STEP2

This feature only needs MDCR_EL3.EnSTEPOP to be written and mdstepop_el1
to be context switched when the next EL is EL1.

Change-Id: I70e2a488f4e50da4b181a0

feat(cpufeat): add support for FEAT_STEP2

This feature only needs MDCR_EL3.EnSTEPOP to be written and mdstepop_el1
to be context switched when the next EL is EL1.

Change-Id: I70e2a488f4e50da4b181a00648c4f608e1da451c
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(cpufeat): remove the feature list from arch_features.h

A much more detailed list is present in docs/architecture_features.rst.

Change-Id: I4cc0a5d387d6b224a8cce7321c892c78be288a4f
Signed-off-by

fix(cpufeat): remove the feature list from arch_features.h

A much more detailed list is present in docs/architecture_features.rst.

Change-Id: I4cc0a5d387d6b224a8cce7321c892c78be288a4f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(build): add size metadata for each vector_entry function

This change adds size metadata for functions created by the
vector_entry/end_vector_entry macros, enabling automated tooling to
know the

feat(build): add size metadata for each vector_entry function

This change adds size metadata for functions created by the
vector_entry/end_vector_entry macros, enabling automated tooling to
know the size of these functions during post processing of an elf
file, for instance.

Change-Id: I760114a46424dc2e16f2749b782bb270cf25cc1b
Signed-off-by: Bill Peckham <bpeckham@google.com>

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feat(morello): add missing is_feat_amu_present_asm function

This function was missed in the last patcheset of
27bc1386f00a2a5089e27ff00f97b41821dc08ed "feat(morello): add Morello
capability enableme

feat(morello): add missing is_feat_amu_present_asm function

This function was missed in the last patcheset of
27bc1386f00a2a5089e27ff00f97b41821dc08ed "feat(morello): add Morello
capability enablement changes"
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/39986

Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
Change-Id: I40d7b334536f43430c22fe18fdf3d972c4995a3a

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feat(crypto): enable floating point register traps in EL3

To prevent the leakage of EL3 information to lower ELs, access to
floating point registers needed to be traped to EL3 unless necessary
(e.g

feat(crypto): enable floating point register traps in EL3

To prevent the leakage of EL3 information to lower ELs, access to
floating point registers needed to be traped to EL3 unless necessary
(e.g the SIMD crypto extension, SIMD context save/restore).

Change-Id: I28a734c43d3e965de87ccc08e99f86669729871f
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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