1 /* 2 * Copyright (c) 2022-2026, Arm Limited. All rights reserved. 3 * Copyright (c) 2023, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef TRAP_HANDLE_H 9 #define TRAP_HANDLE_H 10 11 #include <stdbool.h> 12 #include <context.h> 13 14 #define TRAP_RET_UNHANDLED -1 15 #define TRAP_RET_REPEAT 0 16 #define TRAP_RET_CONTINUE 1 17 18 #define XZR_REG_NUM 31 19 20 /** 21 * handle_sysreg_trap() - Handle AArch64 system register traps from lower ELs 22 * @esr_el3: The content of ESR_EL3, containing the trap syndrome information 23 * @ctx: Pointer to the lower EL context, containing saved registers 24 * 25 * Called by the exception handler when a synchronous trap identifies as a 26 * system register trap (EC=0x18). ESR contains the encoding of the op[x] and 27 * CRm/CRn fields, to identify the system register, and the target/source 28 * GPR plus the direction (MRS/MSR). The lower EL's context can be altered 29 * by the function, to inject back the result of the emulation. 30 * 31 * Return: indication how to proceed with the trap: 32 * TRAP_RET_UNHANDLED(-1): trap is unhandled, trigger panic 33 * TRAP_RET_REPEAT(0): trap was handled, return to the trapping instruction 34 * (repeating it) 35 * TRAP_RET_CONTINUE(1): trap was handled, return to the next instruction 36 * (continuing after it) 37 */ 38 int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx, u_register_t flags); 39 40 /* Handler for injecting UNDEF exception to lower EL */ 41 void inject_undef64(cpu_context_t *ctx); 42 43 u_register_t create_spsr(u_register_t old_spsr, unsigned int target_el); 44 45 /* Prototypes for system register emulation handlers provided by platforms. */ 46 int plat_handle_impdef_trap(uint64_t esr_el3, cpu_context_t *ctx); 47 #if ENABLE_FEAT_RNG_TRAP 48 int plat_handle_rng_trap(uint8_t rt, bool rndrrs, cpu_context_t *ctx); 49 #else 50 static inline int plat_handle_rng_trap(uint8_t rt, bool rndrrs, cpu_context_t *ctx) 51 { 52 return TRAP_RET_UNHANDLED; 53 } 54 #endif 55 56 #endif 57