| 5d5fb10f | 12-Feb-2021 |
Mikael Olsson <mikael.olsson@arm.com> |
plat/arm/juno: Add support to use hw_config in BL31
To make it possible to use the hw_config device tree for dynamic
configuration in BL31 on the Arm Juno platform. A placeholder hw_config
has been
plat/arm/juno: Add support to use hw_config in BL31
To make it possible to use the hw_config device tree for dynamic
configuration in BL31 on the Arm Juno platform. A placeholder hw_config
has been added that is included in the FIP and a Juno specific BL31
setup has been added to populate fconf with the hw_config.
Juno's BL2 setup has been updated to align it with the new behavior
implemented in the Arm FVP platform, where fw_config is passed in arg1
to BL31 instead of soc_fw_config. The BL31 setup is expected to use the
fw_config passed in arg1 to find the hw_config.
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: Ib3570faa6714f92ab8451e8f1e59779dcf19c0b6
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| 69f2ace1 | 30-Mar-2021 |
Usama Arif <usama.arif@arm.com> |
tc0: update GICR base address
The number of ITS have changed from 4 to 1, resulting
in GICR base address change.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I28101f0d1faf9f3c58591b642
tc0: update GICR base address
The number of ITS have changed from 4 to 1, resulting
in GICR base address change.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I28101f0d1faf9f3c58591b642033c3fd49a275e7
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| 4bf98b27 | 12-Feb-2021 |
sah01 <sahil@arm.com> |
fdts: enable virtIO P9 device for morello fvp platform
Signed-off-by: sah01 <sahil@arm.com>
Change-Id: Ic11d739c0bf2076354716cc06fbe25e9000a21e7 |
| a97c390b | 03-Feb-2021 |
Usama Arif <usama.arif@arm.com> |
fdts: use scmi_dvfs clock index 1 for cores 4-7
This allows Matterhorn cores to operate at their optimal OPPs.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I2e1b784da10154a1f1f65dd0e3a
fdts: use scmi_dvfs clock index 1 for cores 4-7
This allows Matterhorn cores to operate at their optimal OPPs.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I2e1b784da10154a1f1f65dd0e3a39213e7683116
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| e5da15e0 | 28-Oct-2020 |
Avinash Mehta <avinash.mehta@arm.com> |
product/tc0: Enable Theodul DSU in TC platform
Increase the core count and add respective entries in DTS.
Add Klein assembly file to cpu sources for core initialization.
Add SCMI entries for cores.
product/tc0: Enable Theodul DSU in TC platform
Increase the core count and add respective entries in DTS.
Add Klein assembly file to cpu sources for core initialization.
Add SCMI entries for cores.
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
Change-Id: I14dc1d87df6dcc8d560ade833ce1f92507054747
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| af99182c | 28-Jan-2021 |
André Przywara <andre.przywara@arm.com> |
Merge "fdts: Fix stdout-path in various platforms" into integration |
| fcb0ea19 | 21-Jan-2021 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
fdts: Fix stdout-path in various platforms
The value of stdout-path is a string and as a result, we can't use a
label as a reference to the serial0 node. This change fixes the
stdout-path property f
fdts: Fix stdout-path in various platforms
The value of stdout-path is a string and as a result, we can't use a
label as a reference to the serial0 node. This change fixes the
stdout-path property for N1SDP, Morello and TC0 by pointing to the
right alias.
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Change-Id: I3d403389a424569be56327fab4140fec06f96d37
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| 2fbb6064 | 29-Jan-2020 |
Ahmad Fatoum <a.fatoum@pengutronix.de> |
fdts: stm32mp1: add support for Linux Automation MC-1 board
The Linux Automation MC-1 is a SBC built around the Octavo Systems
OSD32MP15x SiP. The SiP features up to 1 GB DDR3 RAM, EEPROM and
PMIC.
fdts: stm32mp1: add support for Linux Automation MC-1 board
The Linux Automation MC-1 is a SBC built around the Octavo Systems
OSD32MP15x SiP. The SiP features up to 1 GB DDR3 RAM, EEPROM and
PMIC. The board has eMMC and a SD slot for storage.
The SDRAM calibration values are taken as is from the DKx boards, which
seem to be suitable for operation at German room temperature.
This is deemed ok for now, but for use in the field, the SiP will likely
need to have its timings determined in a climate chamber.
Change-Id: I5f43a61930151ae9d1df2ea7d0f6f9697c813ce0
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
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| b153ce03 | 14-Dec-2020 |
Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> |
fdts: tc0: Add reserved-memory node for OP-TEE
Add reserved-memory region for OP-TEE and mark as no-map. This memory
region is used by OP-TEE as non-secure shared RAM.
Signed-off-by: Arunachalam Ga
fdts: tc0: Add reserved-memory node for OP-TEE
Add reserved-memory region for OP-TEE and mark as no-map. This memory
region is used by OP-TEE as non-secure shared RAM.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I5a22999a8c5550024d0f47e848d35924017df245
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|
| 39460d05 | 17-Nov-2020 |
Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> |
plat: tc0: OP-TEE as S-EL1 SP with SPMC at S-EL2
This patch adds support to enable OP-TEE as S-EL1 SP with SPMC at S-EL2
- create SPMC manifest file with OP-TEE as SP
- add support for ARM
plat: tc0: OP-TEE as S-EL1 SP with SPMC at S-EL2
This patch adds support to enable OP-TEE as S-EL1 SP with SPMC at S-EL2
- create SPMC manifest file with OP-TEE as SP
- add support for ARM_SPMC_MANIFEST_DTS build option
- add optee entry with ffa as method in tc0.dts
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Ia9b5c22c6f605d3886914bbac8ac45e8365671cb
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| 76d22f06 | 03-Dec-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
spm: move OP-TEE SP manifest DTS to FVP platform
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I0981c43e2ef8172138f65d95eac7b20f8969394e |
| 3ac8680c | 12-Nov-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
spm: update OP-TEE SP manifest with device-regions node
Specify peripherals accessed by OP-TEE as a Secure Partition
running as a VM managed by the SPMC.
Signed-off-by: Olivier Deprez <olivier.depr
spm: update OP-TEE SP manifest with device-regions node
Specify peripherals accessed by OP-TEE as a Secure Partition
running as a VM managed by the SPMC.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Icf9aae038e2b1b0ce4696f78ff964bfff8a1498c
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|
| de7091a1 | 25-Oct-2020 |
Jessica Clarke <jrtc27@jrtc27.com> |
fdts: Add VirtIO network device to Morello FVP
Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Change-Id: I5ad5290925f637b94168b507b3dcbdd5e1b82e5a |
| 5c336e06 | 25-Oct-2020 |
Jessica Clarke <jrtc27@jrtc27.com> |
fdts: Remove "virtio-rng" from Morello FVP
This is not a standard string that any kernel recognises, nor do any of
the FDTs embedded in kernels specify this, nor does QEMU's virt machine.
Whilst its
fdts: Remove "virtio-rng" from Morello FVP
This is not a standard string that any kernel recognises, nor do any of
the FDTs embedded in kernels specify this, nor does QEMU's virt machine.
Whilst its presence does no harm, it's not a thing code should consult
as a result, and so drop it in order to not cause confusion and risk
incorrect code being written to search for it.
Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Change-Id: Iea3214a23181c54e600cf8f4f12dfc822140c23d
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|
| a3ecbb35 | 22-Sep-2020 |
Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> |
plat: tc0: Add TZC DRAM1 region for SPMC and trusted OS
- Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for TC0_TZC_DRAM1
- Add TC0_NS_DRAM1 base and mapping
- Reserve memory region in tc0.dts
Change-Id
plat: tc0: Add TZC DRAM1 region for SPMC and trusted OS
- Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for TC0_TZC_DRAM1
- Add TC0_NS_DRAM1 base and mapping
- Reserve memory region in tc0.dts
Change-Id: If2431f7f68e4255e28c86a0e89637dab7c424a13
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
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|
| b37b52ef | 13-Oct-2020 |
Yann Gautier <yann.gautier@st.com> |
fdts: add missing hash node in STM32MP157C-ED1 board DT
Without this node, the board fails to boot and panics in the function
stm32mp_init_auth().
Change-Id: Ia54924410dac2a8c94dd6e45d7e93977fe7d87
fdts: add missing hash node in STM32MP157C-ED1 board DT
Without this node, the board fails to boot and panics in the function
stm32mp_init_auth().
Change-Id: Ia54924410dac2a8c94dd6e45d7e93977fe7d87e2
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 0c3e8acb | 16-Jul-2020 |
Christophe Kerello <christophe.kerello@st.com> |
drivers: stm32_fmc2_nand: move to new bindings
FMC node bindings are modified to add EBI controller node.
FMC driver and associated device tree files are modified
to support these new bindings.
Cha
drivers: stm32_fmc2_nand: move to new bindings
FMC node bindings are modified to add EBI controller node.
FMC driver and associated device tree files are modified
to support these new bindings.
Change-Id: I4bf201e96a1aca20957e0dac3a3b87caadd05bdc
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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|
| 390181a4 | 07-Oct-2020 |
Jagadeesh Ujja <jagadeesh.ujja@arm.com> |
fdts: enable virtio-rng component for morello fvp platform
enable virtio-rng component for morello fvp platform
Change-Id: I89b950f067a4d14dfa418de3859c88c8f91cf7c5
Signed-off-by: Jagadeesh Ujja <j
fdts: enable virtio-rng component for morello fvp platform
enable virtio-rng component for morello fvp platform
Change-Id: I89b950f067a4d14dfa418de3859c88c8f91cf7c5
Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com>
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|
| dc57bea0 | 02-Oct-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fdts: stm32mp1: realign device tree with kernel" into integration |
| 2173b3e0 | 30-Sep-2020 |
André Przywara <andre.przywara@arm.com> |
Merge changes from topic "fpga_generic" into integration
* changes:
arm_fpga: Add platform documentation
arm_fpga: Add post-build linker script
arm_fpga: Add ROM trampoline
arm_fpga: Add dev
Merge changes from topic "fpga_generic" into integration
* changes:
arm_fpga: Add platform documentation
arm_fpga: Add post-build linker script
arm_fpga: Add ROM trampoline
arm_fpga: Add devicetree file
arm_fpga: Remove SPE PMU DT node if SPE is not available
arm_fpga: Adjust GICR size in DT to match number of cores
fdt: Add function to adjust GICv3 redistributor size
drivers: arm: gicv3: Allow detecting number of cores
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| b48883c7 | 03-Aug-2020 |
Andre Przywara <andre.przywara@arm.com> |
arm_fpga: Add devicetree file
The FPGA images used in Arm Ltd. focus on CPU cores, so they share a
common platform, with a minimal set of peripherals (interconnect, GIC,
UART).
This allows to suppor
arm_fpga: Add devicetree file
The FPGA images used in Arm Ltd. focus on CPU cores, so they share a
common platform, with a minimal set of peripherals (interconnect, GIC,
UART).
This allows to support most platforms with a single devicetree file.
The topology and number of CPU cores differ, but those will added at
runtime, in BL31. Other adjustments (GICR size, SPE node, command line)
are also done at this point.
Add the common devicetree file to TF-A's build system, so it can be
build together with BL31. At runtime, the resulting .dtb file should be
uploaded to the address given with FPGA_PRELOADED_DTB_BASE at build time.
Change-Id: I3206d6131059502ec96896e95329865452c9d83e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| e1cbcf96 | 31-Jul-2020 |
Manoj Kumar <manoj.kumar3@arm.com> |
fdts: add device tree sources for morello platform
Change-Id: Ib5945c37983505f327a195bdb8b91ed1b7b90921
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com> |
| 277d6af5 | 18-Sep-2020 |
Yann Gautier <yann.gautier@st.com> |
fdts: stm32mp1: realign device tree with kernel
There is one dtsi file per SoC version:
- STM32MP151: common part for all version, Single Cortex-A7
- STM32MP153: Dual Cortex-A7
- STM32MP157: + GPU a
fdts: stm32mp1: realign device tree with kernel
There is one dtsi file per SoC version:
- STM32MP151: common part for all version, Single Cortex-A7
- STM32MP153: Dual Cortex-A7
- STM32MP157: + GPU and DSI, but not needed for TF-A
The STM32MP15xC include a cryptography peripheral, add it in a dedicated
file.
There are 4 packages available, for which the IOs number change. Have one
file for each package. The 2 packages AB and AD are added.
STM32157A-DK1 and STM32MP157C-DK2 share most of their features, a common
dkx file is then created.
Some reordering is done in other files, and realign with kernel DT files.
The DDR files are generated with our internal tool, no changes in the
registers values.
Change-Id: I9f2ef00306310abe34b94c2f10fc7a77a10493d1
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 8f734c65 | 18-Aug-2020 |
Usama Arif <usama.arif@arm.com> |
fdts: tc0: update MHUv2 interrupt number
This is as part of the architecture change in TC0.
Change-Id: I470241f67938e7998941d26f0e8bc05073234152
Signed-off-by: Usama Arif <usama.arif@arm.com> |
| 35d626bb | 31-Jul-2020 |
Sayanta Pattanayak <sayanta.pattanayak@arm.com> |
n1sdp: add support for remote chip pcie.
Remote chip ITS, SMMU, PCIe nodes are added for enabling remote
chip PCIe hierarchy.
Change-Id: I5b3ca733715defa38e413588ccd13d0688cba271
Signed-off-by: Sa
n1sdp: add support for remote chip pcie.
Remote chip ITS, SMMU, PCIe nodes are added for enabling remote
chip PCIe hierarchy.
Change-Id: I5b3ca733715defa38e413588ccd13d0688cba271
Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
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