| eb9da9e1 | 13-Mar-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge pull request #1856 from masahisak/synquacer-scmi-support
plat/synquacer: enable SCMI support |
| f5ba408c | 08-Mar-2019 |
Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: QSPI boot enablement Manages QSPI initialization, configuration and IO handling as boot device
Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
| b67d2029 | 07-Mar-2019 |
Masahisa Kojima <masahisa.kojima@linaro.org> |
plat/synquacer: enable SCMI support
Enable the SCMI protocol support in SynQuacer platform. Aside from power domain, system power and apcore management protocol, this commit adds the vendor specific
plat/synquacer: enable SCMI support
Enable the SCMI protocol support in SynQuacer platform. Aside from power domain, system power and apcore management protocol, this commit adds the vendor specific protocol(0x80). This vendor specific protocol is used to get the dram mapping information from SCP.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
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| 7d721816 | 06-Mar-2019 |
Paul Beesley <paul.beesley@arm.com> |
drivers: Remove TODO from io_fip.c
The comment suggests checking version numbers and a checksum but there doesn't seem to be any usable data for either of these.
For example, fip_toc_header_t doesn
drivers: Remove TODO from io_fip.c
The comment suggests checking version numbers and a checksum but there doesn't seem to be any usable data for either of these.
For example, fip_toc_header_t doesn't contain any version information and neither does fip_toc_entry_t.
As the function name "is_valid_header" suggests, this function is not concerned with checksumming any of the table of contents entries.
Change-Id: I8673ae5dd37793771760169f26b2f55c15fbf587 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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| 9a2fffb8 | 06-Mar-2019 |
Paul Beesley <paul.beesley@arm.com> |
drivers: Remove TODO from io_storage
This TODO was added five years ago so I assume that there is not going to be a shutdown API added after all.
Change-Id: If0f4e2066454df773bd9bf41ed65d3a10248a2d
drivers: Remove TODO from io_storage
This TODO was added five years ago so I assume that there is not going to be a shutdown API added after all.
Change-Id: If0f4e2066454df773bd9bf41ed65d3a10248a2d3 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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| 3d0f30bb | 12-Mar-2019 |
Tien Hock, Loh <tien.hock.loh@intel.com> |
drivers: synopsys: Fix synopsys MMC driver
There are some issues with synopsys MMC driver: - CMD8 should not expect data (for SD) - ACMD51 should expect data (Send SCR for SD) - dw_prepare should no
drivers: synopsys: Fix synopsys MMC driver
There are some issues with synopsys MMC driver: - CMD8 should not expect data (for SD) - ACMD51 should expect data (Send SCR for SD) - dw_prepare should not dictate size to be MMC_BLOCK_SIZE, block size is now handled in the dw_prepare function - after the CMD completes, when doing dw_read, we need to invalidate cache and wait for the data transfer to complete - Need to set FIFO threshold, otherwise DMA might never get the interrupt to read or write
Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
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| b248bb4a | 08-Mar-2019 |
Yann Gautier <yann.gautier@st.com> |
mmc: stm32_sdmmc2: fill ocr_voltage
STM32MP1 SDMMC device voltage is 3.3V. We should then precise the 2 ranges 3.2 to 3.3V and 3.3 to 3.4V in ocr_voltage field.
Change-Id: I88e479f8f16bfe608a7808ea
mmc: stm32_sdmmc2: fill ocr_voltage
STM32MP1 SDMMC device voltage is 3.3V. We should then precise the 2 ranges 3.2 to 3.3V and 3.3 to 3.4V in ocr_voltage field.
Change-Id: I88e479f8f16bfe608a7808eace0df3fdec48deab Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 3c652a2d | 08-Mar-2019 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1863 from thloh85-intel/mmc_fixes
drivers: mmc: Fix some issues with MMC stack |
| a468e756 | 07-Mar-2019 |
Tien Hock, Loh <tien.hock.loh@intel.com> |
drivers: mmc: Fix some issues with MMC stack
Some bugs in MMC stack needs to be fixed: - scr cannot be local as this will cause cache issue when invalidating after the read DMA transfer is completed
drivers: mmc: Fix some issues with MMC stack
Some bugs in MMC stack needs to be fixed: - scr cannot be local as this will cause cache issue when invalidating after the read DMA transfer is completed - ACMD41 needs to send voltage information in initialization, otherwise the command is a query, thus will not initialize the controller - when checking device state, retry until the retries counter goes to zero before failing
Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
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| f009c5f3 | 05-Mar-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1847 from jts-arm/mbedtls
Remove Mbed TLS dependency from plat_bl_common.c |
| 9b70cd5f | 02-Mar-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
rcar_gen3: drivers: pfc: Configure GP5_09 as input on ULCB
Configure the GPIO5 09 pin as input on the ULCB board by default, since the pin is routed on the expansion connector and not connected to a
rcar_gen3: drivers: pfc: Configure GP5_09 as input on ULCB
Configure the GPIO5 09 pin as input on the ULCB board by default, since the pin is routed on the expansion connector and not connected to anything by default.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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| 845d8fbb | 25-Feb-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
rcar_gen3: Add M3-W 3.0 support
Add support for the M3W 3.0 SoC and synchronize the upstream ATF with Renesas downstream ATF release v2.0.1.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.co
rcar_gen3: Add M3-W 3.0 support
Add support for the M3W 3.0 SoC and synchronize the upstream ATF with Renesas downstream ATF release v2.0.1.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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| 17e1335c | 28-Feb-2019 |
John Tsichritzis <john.tsichritzis@arm.com> |
Remove Mbed TLS dependency from plat_bl_common.c
Due to the shared Mbed TLS heap optimisation introduced in 6d01a463, common code files were depending on Mbed TLS specific headers. This dependency i
Remove Mbed TLS dependency from plat_bl_common.c
Due to the shared Mbed TLS heap optimisation introduced in 6d01a463, common code files were depending on Mbed TLS specific headers. This dependency is now removed by moving the default, unoptimised heap implementation inside the Mbed TLS specific files.
Change-Id: I11ea3eb4474f0d9b6cb79a2afd73a51a4a9b8994 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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| 73308618 | 28-Feb-2019 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Minor changes to documentation and comments
Fix some typos and clarify some sentences.
Change-Id: Id276d1ced9a991b4eddc5c47ad9a825e6b29ef74 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.co
Minor changes to documentation and comments
Fix some typos and clarify some sentences.
Change-Id: Id276d1ced9a991b4eddc5c47ad9a825e6b29ef74 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| 2c8ef2ae | 12-Feb-2019 |
Ying-Chun Liu (PaulLiu) <paulliu@debian.org> |
rpi3: sdhost: SDHost driver improvement
This commit improves the SDHost driver for RPi3 as following: * Unblock MMC_CMD(17). Using MMC_CMD(17) is more efficient on block reading. * In some low
rpi3: sdhost: SDHost driver improvement
This commit improves the SDHost driver for RPi3 as following: * Unblock MMC_CMD(17). Using MMC_CMD(17) is more efficient on block reading. * In some low probability that SEND_OP_COND might results CRC7 error. We can consider that the command runs correctly. We don't need to retry this command so removing the code for retry. * Using MMC_BUS_WIDTH_1 as MMC default value to improve the stability. * Increase the clock to 50Mhz in data mode to speed up the io. * Change the pull resistors configuration to gain more stability.
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
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| ab3d2247 | 22-Feb-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1836 from Yann-lms/docs_and_m4
Update documentation for STM32MP1 and add Cortex-M4 support |
| b053a22e | 15-Feb-2019 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: add minimal support for co-processor Cortex-M4
STM32MP1 chip embeds a dual Cortex-A7 and a Cortex-M4. The support for Cortex-M4 clocks is added when configuring the clock tree. Some minima
stm32mp1: add minimal support for co-processor Cortex-M4
STM32MP1 chip embeds a dual Cortex-A7 and a Cortex-M4. The support for Cortex-M4 clocks is added when configuring the clock tree. Some minimal security features to allow communications between A7 and M4 are also added.
Change-Id: I60417e244a476f60a2758f4969700b2684056665 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| a5aa25af | 12-Dec-2018 |
Usama Arif <usama.arif@arm.com> |
Division functionality for cores that dont have divide hardware.
Cortex a5 doesnt support hardware division such as sdiv and udiv commands. This commit adds a software division function in assembly
Division functionality for cores that dont have divide hardware.
Cortex a5 doesnt support hardware division such as sdiv and udiv commands. This commit adds a software division function in assembly as well as include appropriate files for software divison.
The software division algorithm is a modified version obtained from: http://www.keil.com/support/man/docs/armasm/armasm_dom1359731155623.htm
Change-Id: Ib405a330da5f1cea1e68e07e7b520edeef9e2652 Signed-off-by: Usama Arif <usama.arif@arm.com>
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| 0d21680c | 14-Feb-2019 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: update clock driver
Remove useless private structure in function prototypes. Add a reference counter on clocks. Prepare for future secured/shared/non-secured clocks.
Change-Id: I3dbed8172
stm32mp1: update clock driver
Remove useless private structure in function prototypes. Add a reference counter on clocks. Prepare for future secured/shared/non-secured clocks.
Change-Id: I3dbed81721da5ceff5e10b2c4155b1e340c036ee Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
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| 5202cb39 | 14-Feb-2019 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: add timeout detection in reset driver
This change makes the platform to panic in case of peripheral reset resource malfunction.
Change-Id: I17eb9cb045b78a4e5142a8c33b744e84992d732a Signed
stm32mp1: add timeout detection in reset driver
This change makes the platform to panic in case of peripheral reset resource malfunction.
Change-Id: I17eb9cb045b78a4e5142a8c33b744e84992d732a Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
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| 7ae58c6b | 14-Feb-2019 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: use functions to retrieve some peripheral addresses
PWR, RCC, DDRPHYC & DDRCTRL addresses can be retrieved from device tree. Platform asserts the value read from the DT are the SoC address
stm32mp1: use functions to retrieve some peripheral addresses
PWR, RCC, DDRPHYC & DDRCTRL addresses can be retrieved from device tree. Platform asserts the value read from the DT are the SoC addresses.
Change-Id: I43f0890b51918a30c87ac067d3780ab27a0f59de Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
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| 447b2b13 | 14-Feb-2019 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: split clkfunc code
Create a new file stm32mp_clkfunc.c to put functions that could be common between several platforms.
Change-Id: Ica915c796b162b2345056b33328acc05035a242c Signed-off-by:
stm32mp1: split clkfunc code
Create a new file stm32mp_clkfunc.c to put functions that could be common between several platforms.
Change-Id: Ica915c796b162b2345056b33328acc05035a242c Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| d82d4ff0 | 14-Feb-2019 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: update I2C and PMIC drivers
Regulator configuration at boot takes more information from DT. I2C configuration from DT is done in I2C driver. I2C driver manages more transfer modes. The min
stm32mp1: update I2C and PMIC drivers
Regulator configuration at boot takes more information from DT. I2C configuration from DT is done in I2C driver. I2C driver manages more transfer modes. The min voltage of buck1 should also be increased to 1.2V, else the platform does not boot.
Heavily modifies stm32_i2c.c since many functions move inside the source file to remove redundant declarations.
Change-Id: I0bee5d776cf3ff15e687427cd6abc06ab237d025 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
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| dfdb057a | 14-Feb-2019 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: use new functions to manage timeouts
Remove the previously use function: get_timer, and use new functions timeout_init_us and timeout_elapsed.
Change-Id: I4e95b123648bff7ca91e40462a2a3ae2
stm32mp1: use new functions to manage timeouts
Remove the previously use function: get_timer, and use new functions timeout_init_us and timeout_elapsed.
Change-Id: I4e95b123648bff7ca91e40462a2a3ae24cfe1697 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
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| e0a8ce5d | 14-Feb-2019 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: remove some dependencies on clocks and reset in drivers
Include all RCC, clocks and reset headers from stm32mp1_def.h which if exported to the firmware through platform_def.h. The same dep
stm32mp1: remove some dependencies on clocks and reset in drivers
Include all RCC, clocks and reset headers from stm32mp1_def.h which if exported to the firmware through platform_def.h. The same dependency removal is done in common code as well. Some useless includes are also removed in stm32_sdmmc2 driver.
Change-Id: I731ea5775c3fdb7f7b0c388b93923ed5e84b8d3f Signed-off-by: Yann Gautier <yann.gautier@st.com>
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