| 620dd58b | 31-Oct-2019 |
Deepika Bhavnani <deepika.bhavnani@arm.com> |
SMMUv3:Changed retry loop to delay timer(GENFW-3329)
Instead of retry polling, timer of 1ms is used to poll
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I7e028dc68138d2888e
SMMUv3:Changed retry loop to delay timer(GENFW-3329)
Instead of retry polling, timer of 1ms is used to poll
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I7e028dc68138d2888e3cf0cbed744f5e6bc6ff42
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| 38d5e150 | 08-Oct-2019 |
Avinash Mehta <avinash.mehta@arm.com> |
Correct UART PL011 initialization calculation
Currently for Armv7 plaforms the quotient calculated in pl011
uart init code is moved to register r1.
This patch moves the quotient to register r2 as d
Correct UART PL011 initialization calculation
Currently for Armv7 plaforms the quotient calculated in pl011
uart init code is moved to register r1.
This patch moves the quotient to register r2 as done for other
platforms in the udiv instruction. Value of register r2 is then
used to calculate the values for IBRD and FBRD register
Change-Id: Ie6622f9f0e6d634378b471df5d02823b492c8a24
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
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| 243b61d1 | 11-Sep-2019 |
Nicolas Le Bayon <nicolas.le.bayon@st.com> |
gpio: stm32_gpio: do not mix error code types
Change-Id: I84f8a99be2dcdf7c51fbecdb324df8e2f32cc855
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier
gpio: stm32_gpio: do not mix error code types
Change-Id: I84f8a99be2dcdf7c51fbecdb324df8e2f32cc855
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 57f4b6f8 | 16-Aug-2019 |
Yann Gautier <yann.gautier@st.com> |
mmc: increase delay between ACMD41 retries
In the SD Specification, Power Up Diagram of Card figure, the Timeout
value for initialization process (ACMD41 command retries) is 1 second.
Align to match
mmc: increase delay between ACMD41 retries
In the SD Specification, Power Up Diagram of Card figure, the Timeout
value for initialization process (ACMD41 command retries) is 1 second.
Align to match MMC cards (in mmc_send_op_cond()) and Linux kernel code,
and set the delay between ACMD41 command retries to 10ms.
Change-Id: I2e07cb9944e7d7b72f2d4b13e0505e6751458091
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| ace23683 | 27-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "ld/stm32-authentication" into integration
* changes:
stm32mp1: add authentication support for stm32image
bsec: move bsec_mode_is_closed_device() service to platform
c
Merge changes from topic "ld/stm32-authentication" into integration
* changes:
stm32mp1: add authentication support for stm32image
bsec: move bsec_mode_is_closed_device() service to platform
crypto: stm32_hash: Add HASH driver
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| f7fa5289 | 27-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "amlogic-g12a" into integration
* changes:
amlogic: g12a: Add support for the S905X2 (G12A) platform
amlogic: makefile: Use PLAT variable when possible
amlogic: sha_dm
Merge changes from topic "amlogic-g12a" into integration
* changes:
amlogic: g12a: Add support for the S905X2 (G12A) platform
amlogic: makefile: Use PLAT variable when possible
amlogic: sha_dma: Move register mappings to platform header
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| 1ec39193 | 27-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "GICv3 driver: Fix support for full SPI range" into integration |
| 41bda863 | 27-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "mp/giv3-discovery" into integration
* changes:
Migrate ARM platforms to use the new GICv3 API
Adding new optional PSCI hook pwr_domain_on_finish_late
GICv3: Enable mu
Merge changes from topic "mp/giv3-discovery" into integration
* changes:
Migrate ARM platforms to use the new GICv3 API
Adding new optional PSCI hook pwr_domain_on_finish_late
GICv3: Enable multi socket GIC redistributor frame discovery
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| 69ef7b7f | 26-Sep-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge changes I0283fc2e,Ib476d024,Iada05f7c into integration
* changes:
hikey: fix to load FIP by partition table.
hikey960: fix to load FIP by partition table
drivers: partition: support diff
Merge changes I0283fc2e,Ib476d024,Iada05f7c into integration
* changes:
hikey: fix to load FIP by partition table.
hikey960: fix to load FIP by partition table
drivers: partition: support different block size
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| ec834925 | 15-May-2019 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
GICv3: Enable multi socket GIC redistributor frame discovery
This patch provides declaration and definition of new GICv3 driver
API: gicv3_rdistif_probe().This function delegates the responsibility
GICv3: Enable multi socket GIC redistributor frame discovery
This patch provides declaration and definition of new GICv3 driver
API: gicv3_rdistif_probe().This function delegates the responsibility
of discovering the corresponding Redistributor base frame to each CPU
itself. It is a modified version of gicv3_rdistif_base_addrs_probe()
and is executed by each CPU in the platform unlike the previous
approach in which only the Primary CPU did the discovery of all the
Redistributor frames for every CPU.
The flush operations as part of gicv3_driver_init() function are
made necessary even for platforms with WARMBOOT_ENABLE_DCACHE_EARLY
because the GICv3 driver data structure contents are accessed by CPU
with D-Cache turned off during power down operations.
Change-Id: I1833e81d3974b32a3e4a3df4766a33d070982268
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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| 4bdb1a7a | 03-Sep-2019 |
Lionel Debieve <lionel.debieve@st.com> |
stm32mp1: add authentication support for stm32image
This commit adds authentication binary support for STM32MP1.
It prints the bootrom authentication result if signed
image is used and authenticates
stm32mp1: add authentication support for stm32image
This commit adds authentication binary support for STM32MP1.
It prints the bootrom authentication result if signed
image is used and authenticates the next loaded STM32 images.
It also enables the dynamic translation table support
(PLAT_XLAT_TABLES_DYNAMIC) to use bootrom services.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Iba706519e0dc6b6fae1f3dd498383351f0f75f51
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| f700423c | 16-Sep-2019 |
Lionel Debieve <lionel.debieve@st.com> |
bsec: move bsec_mode_is_closed_device() service to platform
This BSEC service is a platform specific service. Implementation
moved to the platform part.
Signed-off-by: Lionel Debieve <lionel.debiev
bsec: move bsec_mode_is_closed_device() service to platform
This BSEC service is a platform specific service. Implementation
moved to the platform part.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I1f70ed48a446860498ed111acce01187568538c9
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| b1e0b11c | 26-Aug-2019 |
Lionel Debieve <lionel.debieve@st.com> |
crypto: stm32_hash: Add HASH driver
The driver manages the HASH processor IP on STM32MP1
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I3b67c80c16d819f86b951dae29a6c465e51ad585 |
| f8631f51 | 14-Sep-2019 |
Haojian Zhuang <haojian.zhuang@linaro.org> |
drivers: partition: support different block size
The block size of some storage device is 4096-byte long, such as UFS. But
PARTITION_BLOCK_SIZE is defined as 512-byte long. So replace it by
PLAT_PAR
drivers: partition: support different block size
The block size of some storage device is 4096-byte long, such as UFS. But
PARTITION_BLOCK_SIZE is defined as 512-byte long. So replace it by
PLAT_PARTITION_BLOCK_SIZE. Make it configurable in platform.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Change-Id: Iada05f7c646d0a0f2c0d3b8545540b3cb7153de3
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|
| 26d94393 | 18-Sep-2019 |
Carlo Caione <ccaione@baylibre.com> |
amlogic: sha_dma: Move register mappings to platform header
The registers location for the SHA DMA driver is not unique for the
different platforms. Move the mapping out of the driver and into the
p
amlogic: sha_dma: Move register mappings to platform header
The registers location for the SHA DMA driver is not unique for the
different platforms. Move the mapping out of the driver and into the
platform-specific header.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ice64637844a3cb384b01e466cb8c1cea5f764129
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|
| 990ab78e | 09-Jul-2019 |
Andre Przywara <andre.przywara@arm.com> |
rpi3: Move rng driver to drivers
To allow sharing the driver between the RPi3 and RPi4, move the random
number generator driver into the generic driver directory.
Change-Id: Iae94d7cb22c6bce3af9bff
rpi3: Move rng driver to drivers
To allow sharing the driver between the RPi3 and RPi4, move the random
number generator driver into the generic driver directory.
Change-Id: Iae94d7cb22c6bce3af9bff709d76d4caf87b14d1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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|
| c0031189 | 09-Jul-2019 |
Andre Przywara <andre.przywara@arm.com> |
rpi3: Move VC mailbox driver into generic drivers directory
To allow sharing the driver between the RPi3 and RPi4, move the mailbox
driver into the generic driver directory.
Change-Id: I463e49acf82
rpi3: Move VC mailbox driver into generic drivers directory
To allow sharing the driver between the RPi3 and RPi4, move the mailbox
driver into the generic driver directory.
Change-Id: I463e49acf82b02bf004f3d56482b7791f3020bc0
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| eb5f0ba4 | 13-Sep-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
GICv3 driver: Fix support for full SPI range
This patch fixes GICv3 driver bug which causes assertion
when full range of SPI INTIDs 32-1019 is supported in
GICv3 implementation.
Change-Id: Ib6da4b6
GICv3 driver: Fix support for full SPI range
This patch fixes GICv3 driver bug which causes assertion
when full range of SPI INTIDs 32-1019 is supported in
GICv3 implementation.
Change-Id: Ib6da4b6eea868cff271cb32c7c7570bf5547ab47
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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|
| 42cdeb93 | 13-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "stm32mp1: manage CONSOLE_FLAG_TRANSLATE_CRLF and cleanup driver" into integration |
| 6a415a50 | 09-Sep-2019 |
Justin Chadwell <justin.chadwell@arm.com> |
Remove RSA PKCS#1 v1.5 support from cert_tool
Support for PKCS#1 v1.5 was deprecated in SHA 1001202 and fully removed
in SHA fe199e3, however, cert_tool is still able to generate
certificates in tha
Remove RSA PKCS#1 v1.5 support from cert_tool
Support for PKCS#1 v1.5 was deprecated in SHA 1001202 and fully removed
in SHA fe199e3, however, cert_tool is still able to generate
certificates in that form. This patch fully removes the ability for
cert_tool to generate these certificates.
Additionally, this patch also fixes a bug where the issuing certificate
was a RSA and the issued certificate was EcDSA. In this case, the issued
certificate would be signed using PKCS#1 v1.5 instead of RSAPSS per
PKCS#1 v2.1, preventing TF-A from verifying the image signatures. Now
that PKCS#1 v1.5 support is removed, all certificates that are signed
with RSA now use the more modern padding scheme.
Change-Id: Id87d7d915be594a1876a73080528d968e65c4e9a
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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| aacff749 | 29-Jul-2019 |
Justin Chadwell <justin.chadwell@arm.com> |
Support larger RSA key sizes when using MBEDTLS
Previously, TF-A could not support large RSA key sizes as the
configuration options passed to MBEDTLS prevented storing and performing
calculations wi
Support larger RSA key sizes when using MBEDTLS
Previously, TF-A could not support large RSA key sizes as the
configuration options passed to MBEDTLS prevented storing and performing
calculations with the larger, higher-precision numbers required. With
these changes to the arguments passed to MBEDTLS, TF-A now supports
using 3072 (3K) and 4096 (4K) keys in certificates.
Change-Id: Ib73a6773145d2faa25c28d04f9a42e86f2fd555f
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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| f38e5182 | 12-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes I072c0f61,I798401f4,I9648ef55,I7225d9fa,Ife682288, ... into integration
* changes:
rcar_gen3: drivers: ddr_b: Update DDR setting for H3, M3, M3N
rcar_gen3: drivers: qos: update QoS
Merge changes I072c0f61,I798401f4,I9648ef55,I7225d9fa,Ife682288, ... into integration
* changes:
rcar_gen3: drivers: ddr_b: Update DDR setting for H3, M3, M3N
rcar_gen3: drivers: qos: update QoS setting
rcar_gen3: drivers: ddr_b: Fix checkpatch errors in headers
rcar_gen3: drivers: ddr_b: Fix line-over-80s
rcar_gen3: drivers: ddr_b: Further checkpatch cleanups
rcar_gen3: drivers: ddr_b: Clean up camel case
rcar_get3: drivers: ddr_b: Basic checkpatch fixes
rcar_get3: drivers: ddr: Partly unify register macros between DDR A and B
rcar_get3: drivers: ddr: Clean up common code
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| 9af73b36 | 12-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "amlogic-refactoring" into integration
* changes:
amlogic: Fix includes order
amlogic: Fix header guards
amlogic: Fix prefixes in the SoC specific files
amlogic: Fix
Merge changes from topic "amlogic-refactoring" into integration
* changes:
amlogic: Fix includes order
amlogic: Fix header guards
amlogic: Fix prefixes in the SoC specific files
amlogic: Fix prefixes in the PM code
amlogic: Fix prefixes in the SCPI related code
amlogic: Fix prefixes in the MHU code
amlogic: Fix prefixes in the SIP/SVC code
amlogic: Fix prefixes in the thermal driver
amlogic: Fix prefixes in the private header file
amlogic: Fix prefixes in the efuse driver
amlogic: Fix prefixes in the platform macros file
amlogic: Fix prefixes in the helpers file
amlogic: Rework Makefiles
amlogic: Move the SIP SVC code to common directory
amlogic: Move topology file to common directory
amlogic: Move thermal code to common directory
amlogic: Move MHU code to common directory
amlogic: Move efuse code to common directory
amlogic: Move platform macros assembly file to common directory
amlogic: Introduce unified private header file
amlogic: Move SCPI code to common directory
amlogic: Move the SHA256 DMA driver to common directory
amlogic: Move assembly helpers to common directory
amlogic: Introduce directory parameters in the makefiles
meson: Rename platform directory to amlogic
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| ebf851ed | 04-Sep-2019 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: manage CONSOLE_FLAG_TRANSLATE_CRLF and cleanup driver
The STM32 console driver was pre-pending '\r' before '\n'.
It is now managed by the framework with the flag:
CONSOLE_FLAG_TRANSLATE_CR
stm32mp1: manage CONSOLE_FLAG_TRANSLATE_CRLF and cleanup driver
The STM32 console driver was pre-pending '\r' before '\n'.
It is now managed by the framework with the flag:
CONSOLE_FLAG_TRANSLATE_CRLF.
Remove the code in driver, and add the flag for STM32MP1.
Change-Id: I5d0d5d5c4abee0b7dc11c2f8707b1b5cf10149ab
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 01b2a7fc | 24-Aug-2019 |
Carlo Caione <ccaione@baylibre.com> |
amlogic: Move the SHA256 DMA driver to common directory
The SHA256 DMA driver can be used by multiple SoCs. Move it to the
common directory.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Chang
amlogic: Move the SHA256 DMA driver to common directory
The SHA256 DMA driver can be used by multiple SoCs. Move it to the
common directory.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I96319eeeeeebd503ef0dcb07c0e4ff6a67afeaa5
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