driver: brcm: add RNG driver

Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com>
Change-Id: I490d7e4d49bd9f5a62d343a264a1e14c2066ceca

io_fip: return -ENFILE when a file is already open

The cause of failure is not memory shortage.

The comment for ENFILE in include/lib/libc/errno.h

/* Too many open files in system */

... is a b

io_fip: return -ENFILE when a file is already open

The cause of failure is not memory shortage.

The comment for ENFILE in include/lib/libc/errno.h

/* Too many open files in system */

... is a better match to the warning message here.

Change-Id: I45a1740995d464edd8b3e32b93f1f92ba17e5874
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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drivers: marvell: Fix the LLC SRAM driver

- Fix the line address macro
- LLC invalidate and enable before ways lock for allocation
- Add support for limited SRAM size allocation
- Add SRAM RW test f

drivers: marvell: Fix the LLC SRAM driver

- Fix the line address macro
- LLC invalidate and enable before ways lock for allocation
- Add support for limited SRAM size allocation
- Add SRAM RW test function

Change-Id: I1867ece3047566ddd7931bd7472e1f47fb42c8d4
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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drivers: marvell: mg_conf_cm3: pass comphy lane number to AP FW

Since the AP process can be enabled on different setups, the information
about used comphy lane should be passed to AP FW. For instanc

drivers: marvell: mg_conf_cm3: pass comphy lane number to AP FW

Since the AP process can be enabled on different setups, the information
about used comphy lane should be passed to AP FW. For instance:
- A8K development board uses comphy lane 2 for eth 0
- cn913x development board uses comphy lane 4 for eth 0

Change-Id: Icf001fb3eea4d9c24c09384e49844ecaf8655ad2
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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plat: marvell: armada: move mg conf related code to appropriate driver

Now when mg_conf_cm3 driver is present - move all relevant code there.

Change-Id: I444d9e877c450d6ee69ca3a49b547e4c3aeac0be
Si

plat: marvell: armada: move mg conf related code to appropriate driver

Now when mg_conf_cm3 driver is present - move all relevant code there.

Change-Id: I444d9e877c450d6ee69ca3a49b547e4c3aeac0be
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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marvell: comphy: start AP FW when comphy AP mode selected

After configuring comphy to AP mode also start AP FW.

Change-Id: Ib28977d7ee643575a818ba17f69dea0b7e8e0df4
Signed-off-by: Grzegorz Jaszczyk

marvell: comphy: start AP FW when comphy AP mode selected

After configuring comphy to AP mode also start AP FW.

Change-Id: Ib28977d7ee643575a818ba17f69dea0b7e8e0df4
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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drivers: marvell: mg_conf_cm3: add basic driver

Implement function which will allow to start AP FW.

Change-Id: Ie0fc8ad138bf56b10809cdc92d1e5e96a2aaf33f
Signed-off-by: Grzegorz Jaszczyk <jaz@semiha

drivers: marvell: mg_conf_cm3: add basic driver

Implement function which will allow to start AP FW.

Change-Id: Ie0fc8ad138bf56b10809cdc92d1e5e96a2aaf33f
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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io_storage: remove redundant assigments

The assignments to 'result' are unneeded.

Change-Id: I18899f10bf9bd7f219f0e47a981683d8b4701bde
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

drivers/stm32_hash: register resources as secure or not

Register in the shared resources driver the secure or non-secure state
of the HASH instances. Note that only BL32 needs to register the
shared

drivers/stm32_hash: register resources as secure or not

Register in the shared resources driver the secure or non-secure state
of the HASH instances. Note that only BL32 needs to register the
shared peripheral because BL2 does not embed the shared resources
driver.

Change-Id: I7f78fa8e47da71d48ef8b1dfe4d6f040fe918d8b
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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drivers/stm32_gpio: register GPIO resources as secure or not

Register in the shared resources driver the secure or non-secure state
of the GPIO pins.

Change-Id: Ifda473bcbbb0af799be6587961d6641edf8

drivers/stm32_gpio: register GPIO resources as secure or not

Register in the shared resources driver the secure or non-secure state
of the GPIO pins.

Change-Id: Ifda473bcbbb0af799be6587961d6641edf887605
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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drivers/stm32_iwdg: register IWDG resources as secure or not

Register in the shared resources driver the secure or non-secure state
of the IWDG instances.

Change-Id: I3a3bc9525447f6a2a465891ca3a3fd

drivers/stm32_iwdg: register IWDG resources as secure or not

Register in the shared resources driver the secure or non-secure state
of the IWDG instances.

Change-Id: I3a3bc9525447f6a2a465891ca3a3fd5fe664ca07
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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drivers/stm32mp_pmic: register PMIC resources as secure or not

Register in the shared resources driver the secure or non-secure
state of the PMIC.

Change-Id: Ic1f172ba62785018f8e9bb321782d725e2d2f4

drivers/stm32mp_pmic: register PMIC resources as secure or not

Register in the shared resources driver the secure or non-secure
state of the PMIC.

Change-Id: Ic1f172ba62785018f8e9bb321782d725e2d2f434
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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drivers: st: clock: register parent of secure clocks

Introduce stm32mp1_register_clock_parents_secure() in stm32mp1
clock driver to allow platform shared resources to register as
secure the parent c

drivers: st: clock: register parent of secure clocks

Introduce stm32mp1_register_clock_parents_secure() in stm32mp1
clock driver to allow platform shared resources to register as
secure the parent clocks of a clock registered as secure.

Change-Id: I53a9ab6aa78ee840ededce67e7b12a84e08ee843
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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drivers: arm: gicv3: auto-detect presence of GIC600-AE

This patch adds the IIDR value for GIC600-AE to the gicv3_is_gic600()
helper function. This helps platforms supporting this version of the
GIC6

drivers: arm: gicv3: auto-detect presence of GIC600-AE

This patch adds the IIDR value for GIC600-AE to the gicv3_is_gic600()
helper function. This helps platforms supporting this version of the
GIC600 interrupt controller to function with the generic GIC driver.

Verified with tftf-validation test suite

******************************* Summary *******************************
> Test suite 'Framework Validation'
Passed
> Test suite 'Timer framework Validation'
Passed
=================================
Tests Skipped : 0
Tests Passed : 6
Tests Failed : 0
Tests Crashed : 0
Total tests : 6
=================================
NOTICE: Exiting tests.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I518ae7b56f7f372e374e453287d76ca370fc3574

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Merge changes Ib9c82b85,Ib348e097,I4dc315e4,I58a8ce44,Iebc03361, ... into integration

* changes:
plat: marvell: armada: a8k: add OP-TEE OS MMU tables
drivers: marvell: add support for mapping th

Merge changes Ib9c82b85,Ib348e097,I4dc315e4,I58a8ce44,Iebc03361, ... into integration

* changes:
plat: marvell: armada: a8k: add OP-TEE OS MMU tables
drivers: marvell: add support for mapping the entire LLC to SRAM
plat: marvell: armada: add LLC SRAM CCU setup for AP806/AP807 platforms
plat: marvell: armada: reduce memory size reserved for FIP image
plat: marvell: armada: platform definitions cleanup
plat: marvell: armada: a8k: check CCU window state before loading MSS BL2
drivers: marvell: add CCU driver API for window state checking
drivers: marvell: align and extend llc macros
plat: marvell: a8k: move address config of cp1/2 to BL2
plat: marvell: armada: re-enable BL32_BASE definition
plat: marvell: a8k: extend includes to take advantage of the phy_porting_layer
marvell: comphy: initialize common phy selector for AP mode
marvell: comphy: update rx_training procedure
plat: marvell: armada: configure amb for all CPs
plat: marvell: armada: modify PLAT_FAMILY name for 37xx SoCs

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fconf: Clean confused naming between TB_FW and FW_CONFIG

Cleaned up confused naming between TB_FW and FW_CONFIG.

Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Signed-off-by: Manish V B

fconf: Clean confused naming between TB_FW and FW_CONFIG

Cleaned up confused naming between TB_FW and FW_CONFIG.

Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I9e9f6e6ca076d38fee0388f97d370431ae067f08

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tbbr/dualroot: Add fw_config image in chain of trust

fw_config image is authenticated using secure boot framework by
adding it into the single root and dual root chain of trust.

The COT for fw_conf

tbbr/dualroot: Add fw_config image in chain of trust

fw_config image is authenticated using secure boot framework by
adding it into the single root and dual root chain of trust.

The COT for fw_config image looks as below:

+------------------+ +-------------------+
| ROTPK/ROTPK Hash |------>| Trusted Boot fw |
+------------------+ | Certificate |
| (Auth Image) |
/+-------------------+
/ |
/ |
/ |
/ |
L v
+------------------+ +-------------------+
| fw_config hash |------>| fw_config |
| | | (Data Image) |
+------------------+ +-------------------+

Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I08fc8ee95c29a95bb140c807dd06e772474c7367

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Merge "TF-A GIC driver: Add barrier before eoi" into integration

Merge changes from topic "scmi-msg" into integration

* changes:
drivers/scmi-msg: smt entry points for incoming messages
drivers/scmi-msg: support for reset domain protocol
drivers/scmi-msg: s

Merge changes from topic "scmi-msg" into integration

* changes:
drivers/scmi-msg: smt entry points for incoming messages
drivers/scmi-msg: support for reset domain protocol
drivers/scmi-msg: support for clock protocol
drivers/scmi-msg: driver for processing scmi messages

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TF-A GIC driver: Add barrier before eoi

It is desired to have the peripheral writes completed to clear the
interrupt condition and de-assert the interrupt request to GIC before
EOI write. Failing wh

TF-A GIC driver: Add barrier before eoi

It is desired to have the peripheral writes completed to clear the
interrupt condition and de-assert the interrupt request to GIC before
EOI write. Failing which spurious interrupt will occurred.

A barrier is needed to ensure peripheral register write transfers are
complete before EOI is done.

GICv2 memory mapped DEVICE nGnR(n)E writes are ordered from core point
of view. However these writes may pass over different interconnects,
bridges, buffers leaving some rare chances for the actual write to
complete out of order.

GICv3 ICC EOI system register writes have no ordering against nGnR(n)E
memory writes as they are over different interfaces.

Hence a dsb can ensure from core no writes are issued before the previous
writes are *complete*.

Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Change-Id: Ie6362009e2f91955be99dca8ece14ade7b4811d6

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drivers: marvell: add support for mapping the entire LLC to SRAM

Add llc_sram_enable() and llc_sram_disable() APIs to Marvell
cache_lls driver.
Add LLC_SRAM definition to Marvell common makefile - d

drivers: marvell: add support for mapping the entire LLC to SRAM

Add llc_sram_enable() and llc_sram_disable() APIs to Marvell
cache_lls driver.
Add LLC_SRAM definition to Marvell common makefile - disabled
by the default.
Add description of LLC_SRAM flag to the build documentation.

Change-Id: Ib348e09752ce1206d29268ef96c9018b781db182
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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drivers: marvell: add CCU driver API for window state checking

Add ccu_is_win_enabled() API for checking the CCU window
state using AP and window indexes.

Change-Id: Ib955a2cac28b2729b0a763f3bbbea2

drivers: marvell: add CCU driver API for window state checking

Add ccu_is_win_enabled() API for checking the CCU window
state using AP and window indexes.

Change-Id: Ib955a2cac28b2729b0a763f3bbbea28b476a2fe4
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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drivers: marvell: align and extend llc macros

Make all LLC-related macros to start with the same prefix
Add more LLC control registers definitions
This patch is a preparation step for LLC SRAM suppo

drivers: marvell: align and extend llc macros

Make all LLC-related macros to start with the same prefix
Add more LLC control registers definitions
This patch is a preparation step for LLC SRAM support

Change-Id: I0a4f0fc83e8ef35be93dd239a85f2a9f88d1ab19
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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marvell: comphy: initialize common phy selector for AP mode

Configuring common phy selector which was missing for AP mode.

Change-Id: I15be1ba50b8aafe9094734abec139d72c18bb224
Signed-off-by: Grzego

marvell: comphy: initialize common phy selector for AP mode

Configuring common phy selector which was missing for AP mode.

Change-Id: I15be1ba50b8aafe9094734abec139d72c18bb224
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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marvell: comphy: update rx_training procedure

1) Relay only on rx training, remove parts responsible for tx training
(trx training).
2) Add extra steps e.g. preconfigure FFE before starting training

marvell: comphy: update rx_training procedure

1) Relay only on rx training, remove parts responsible for tx training
(trx training).
2) Add extra steps e.g. preconfigure FFE before starting training.
3) Remove some unnecessary steps like RRBS31 loopback setting which
shouldn't be relevant for tx_training.

Change-Id: Ib1e8567714f9ce33578186a262c339aa4b1c51f2
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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