Merge changes from topic "stm32mp1_plat_updates" into integration

* changes:
docs: update STM32MP1 with versions details
stm32mp1: get peripheral base address from a define
stm32mp1: add finis

Merge changes from topic "stm32mp1_plat_updates" into integration

* changes:
docs: update STM32MP1 with versions details
stm32mp1: get peripheral base address from a define
stm32mp1: add finished good variant in board identifier

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Merge changes from topic "st/fmc2" into integration

* changes:
drivers: stm32_fmc2_nand: fix boundary check for chip select
drivers: stm32_fmc2_nand: move to new bindings

stm32mp1: get peripheral base address from a define

Retrieve peripheral base address from a define instead of
parsing the device tree. The goal is to improve execution time.

Signed-off-by: Pascal P

stm32mp1: get peripheral base address from a define

Retrieve peripheral base address from a define instead of
parsing the device tree. The goal is to improve execution time.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I2588c53ad3d4abcc3d7fe156458434a7940dd72b

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Increase type widths to satisfy width requirements

Usually, C has no problem up-converting types to larger bit sizes. MISRA
rule 10.7 requires that you not do this, or be very explicit about this.
T

Increase type widths to satisfy width requirements

Usually, C has no problem up-converting types to larger bit sizes. MISRA
rule 10.7 requires that you not do this, or be very explicit about this.
This resolves the following required rule:

bl1/aarch64/bl1_context_mgmt.c:81:[MISRA C-2012 Rule 10.7 (required)]<None>
The width of the composite expression "0U | ((mode & 3U) << 2U) | 1U |
0x3c0U" (32 bits) is less that the right hand operand
"18446744073709547519ULL" (64 bits).

This also resolves MISRA defects such as:

bl2/aarch64/bl2arch_setup.c:18:[MISRA C-2012 Rule 12.2 (required)]
In the expression "3U << 20", shifting more than 7 bits, the number
of bits in the essential type of the left expression, "3U", is
not allowed.

Further, MISRA requires that all shifts don't overflow. The definition of
PAGE_SIZE was (1U << 12), and 1U is 8 bits. This caused about 50 issues.
This fixes the violation by changing the definition to 1UL << 12. Since
this uses 32bits, it should not create any issues for aarch32.

This patch also contains a fix for a build failure in the sun50i_a64
platform. Specifically, these misra fixes removed a single and
instruction,

92407e73 and x19, x19, #0xffffffff

from the cm_setup_context function caused a relocation in
psci_cpus_on_start to require a linker-generated stub. This increased the
size of the .text section and caused an alignment later on to go over a
page boundary and round up to the end of RAM before placing the .data
section. This sectionn is of non-zero size and therefore causes a link
error.

The fix included in this reorders the functions during link time
without changing their ording with respect to alignment.

Change-Id: I76b4b662c3d262296728a8b9aab7a33b02087f16
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

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drivers: stm32_fmc2_nand: fix boundary check for chip select

Chip select is retrieved from device tree and check
must be done regarding the MAX_CS defined.

Signed-off-by: Lionel Debieve <lionel.deb

drivers: stm32_fmc2_nand: fix boundary check for chip select

Chip select is retrieved from device tree and check
must be done regarding the MAX_CS defined.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Reviewed-by: Christophe KERELLO <christophe.kerello@st.com>
Change-Id: I03144b133bd51a845a4794f0f6bbd9402fc04936

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drivers: stm32_fmc2_nand: move to new bindings

FMC node bindings are modified to add EBI controller node.
FMC driver and associated device tree files are modified
to support these new bindings.

Cha

drivers: stm32_fmc2_nand: move to new bindings

FMC node bindings are modified to add EBI controller node.
FMC driver and associated device tree files are modified
to support these new bindings.

Change-Id: I4bf201e96a1aca20957e0dac3a3b87caadd05bdc
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

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Fix casting bug in gicv2_main.c

In the function gicv2_set_spi_routing, the signed value proc_num is cast
to unsigned int before being compared to other unsigned values in two
assert calls. The valu

Fix casting bug in gicv2_main.c

In the function gicv2_set_spi_routing, the signed value proc_num is cast
to unsigned int before being compared to other unsigned values in two
assert calls. The value proc_num can be a negative value, and once the
negative value is cast to unsigned it becomes a very large number which
will trigger the assert. This patch changes the assert cast so that the
unsigned values are cast to signed instead, keeping the same functionality
but allowing proc_num to be negative.

This bug can be seen when running the SDEI RM_ANY routing mode test in
TFTF on the Juno platform.

This patch also makes the usage of the proc_num variable in other gicv2
functions more clear.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: If1b98eebb00bd9b73862e5e995e5e68c168170a6

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Don't return error information from console_flush

And from crash_console_flush.

We ignore the error information return by console_flush in _every_
place where we call it, and casting the return typ

Don't return error information from console_flush

And from crash_console_flush.

We ignore the error information return by console_flush in _every_
place where we call it, and casting the return type to void does not
work around the MISRA violation that this causes. Instead, we collect
the error information from the driver (to avoid changing that API), and
don't return it to the caller.

Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

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drivers: stm32_fmc2_nand: fix incorrect error detection

Clear interrupt flag register after each sector read to avoid
issue when checking the register status.
Without clearing the interrupt, the sta

drivers: stm32_fmc2_nand: fix incorrect error detection

Clear interrupt flag register after each sector read to avoid
issue when checking the register status.
Without clearing the interrupt, the status read doesn't wait
properly the ready bit.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: If290e3f165b986f0e736bb1b5e4d3dad4b749d74

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marvell: comphy: cp110: add support for USB comphy polarity invert

The polarity inversion for USB was not tested due to lack of hw design
which requires it. Currently all supported boards doesn't re

marvell: comphy: cp110: add support for USB comphy polarity invert

The polarity inversion for USB was not tested due to lack of hw design
which requires it. Currently all supported boards doesn't require USB
phy polarity inversion, therefore COMPHY_POLARITY_NO_INVERT is set for
all boards. Enable the option for the ones that need it.

Change-Id: Ia5f2ee313a93962e94963e2dd8a759ef6d9da369
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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marvell: comphy: cp110: add support for SATA comphy polarity invert

The cp110 comphy has ability to invert RX and/or TX polarity. Polarity
depends on board design. Currently all supported boards doe

marvell: comphy: cp110: add support for SATA comphy polarity invert

The cp110 comphy has ability to invert RX and/or TX polarity. Polarity
depends on board design. Currently all supported boards doesn't require
SATA phy polarity invert, therefore COMPHY_POLARITY_NO_INVERT is set for
all boards.

Change-Id: Ifd0bc6aaf8a76a0928132b197422f3193cf020d5
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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marvell: comphy: cp110: implement erratum IPCE_COMPHY-1353

According to erratum IPCE_COMPHY-1353 the TX_IDLE bit should
be toggled in addition to the XFI/SFI PHY reset.

Change-Id: Idd2c2abfcb2f960c

marvell: comphy: cp110: implement erratum IPCE_COMPHY-1353

According to erratum IPCE_COMPHY-1353 the TX_IDLE bit should
be toggled in addition to the XFI/SFI PHY reset.

Change-Id: Idd2c2abfcb2f960caa01e6d69db524c2e4734f50
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

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drivers: marvell: mochi: Update AP incoming masters secure level

Do not force non-secure access level for PIDI masters when LLC_SRAM
is enabled. The EIP197 is located on CP0 and need to access secur

drivers: marvell: mochi: Update AP incoming masters secure level

Do not force non-secure access level for PIDI masters when LLC_SRAM
is enabled. The EIP197 is located on CP0 and need to access secure
SRAM in AP LLC. This requires EIP197 DMA to have AXPROT[1]=0 and not
changed when forwarded to address decoding tables.

Change-Id: I8962db94a124350c14220ba6d0364d294ae4664a
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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plat: marvell: armada: add ccu window for workaround errata-id 3033912

Added ccu window to allow access to addresses
in the range [0xf100_0000, 0xf1ff_ffff].

Change-Id: I63ee68338d674114d01cd627198

plat: marvell: armada: add ccu window for workaround errata-id 3033912

Added ccu window to allow access to addresses
in the range [0xf100_0000, 0xf1ff_ffff].

Change-Id: I63ee68338d674114d01cd627198dc907653493e8
Signed-off-by: Alex Leibovich <alexl@marvell.com>

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Merge "Measured Boot Driver: Fix MISRA-C 2012 defects" into integration

Crypto library: Migrate support to MbedTLS v2.24.0

This patch migrates the mbedcrypto dependency for TF-A
to mbedTLS repo v2.24.0 which is the latest release tag.
The relevant documentation is updat

Crypto library: Migrate support to MbedTLS v2.24.0

This patch migrates the mbedcrypto dependency for TF-A
to mbedTLS repo v2.24.0 which is the latest release tag.
The relevant documentation is updated to reflect the
use of new version.

Change-Id: I116f44242e8c98e856416ea871d11abd3234dac1
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

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drivers: arm: gicv3: Allow detecting number of cores

A GICv3 interrupt controller will be instantiated for a certain number
of cores. This will result in the respective number of GICR frames. The
la

drivers: arm: gicv3: Allow detecting number of cores

A GICv3 interrupt controller will be instantiated for a certain number
of cores. This will result in the respective number of GICR frames. The
last frame will have the "Last" bit set in its GICR_TYPER register.

For platforms with a topology unknown at build time (the Arm FPGAs, for
instance), we need to learn the number of used cores at runtime, to size
the GICR region in the devicetree accordingly.

Add a generic function that iterates over all GICR frames until it
encounters one with the "Last" bit set. It returns the number of cores
the GICv3 has been configured for.

Change-Id: I79f033c50dfc1c275aba7122725868811abcc4f8
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Measured Boot Driver: Fix MISRA-C 2012 defects

This patch fixes MISRA C-2012 Pointers and Arrays
Rule 18.4 defects reported by Coverity scan:
"misra_c_2012_rule_18_4_violation: Using arithmetic on p

Measured Boot Driver: Fix MISRA-C 2012 defects

This patch fixes MISRA C-2012 Pointers and Arrays
Rule 18.4 defects reported by Coverity scan:
"misra_c_2012_rule_18_4_violation: Using arithmetic on pointer "

Change-Id: I06753b28467c473e346b9871c1657284fc43a3f3
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

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Merge changes from topic "stm32_drivers_update" into integration

* changes:
clk: stm32mp1: fix rcc mckprot status
drivers: st: add missing includes in ETZPC header
mmc: st: clear some flags be

Merge changes from topic "stm32_drivers_update" into integration

* changes:
clk: stm32mp1: fix rcc mckprot status
drivers: st: add missing includes in ETZPC header
mmc: st: clear some flags before sending a command
mmc: st: correct retries management
nand: raw_nand: fix timeout issue in nand_wait_ready
mtd: spi_nor: change message level on macronix detection
gpio: stm32_gpio: check GPIO node status after checking DT
crypto: stm32_hash: fix issue when restarting computation

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clk: stm32mp1: fix rcc mckprot status

MCKPROT hardening in RCC mandates that both bits RCC[TZEN] and
RCC[MCKPROT] are enabled. This change fixes stm32mp1_rcc_is_mckprot()
to check both bits, not RCC

clk: stm32mp1: fix rcc mckprot status

MCKPROT hardening in RCC mandates that both bits RCC[TZEN] and
RCC[MCKPROT] are enabled. This change fixes stm32mp1_rcc_is_mckprot()
to check both bits, not RCC[MCKPROT] only.

This change also updates stm32mp1_rcc_is_secure() for consistency.

Change-Id: If1f07babdcb5677906ddbf974d9dc17255d4e174
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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mmc: st: clear some flags before sending a command

The ICR static flags are cleared before sending a command.
The SDMMC_DCTRLR register is set to 0 if no data is expected on a given
command or on th

mmc: st: clear some flags before sending a command

The ICR static flags are cleared before sending a command.
The SDMMC_DCTRLR register is set to 0 if no data is expected on a given
command or on the next command in case of CMD55.

Change-Id: I5ae172a484218f53160e98b3684967c6960475a6
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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mmc: st: correct retries management

The retries number should be 3.
A warning message is added in mmc_block_read(), and the code is refactored.

Change-Id: I577c7dd91c451c7580b1660042cb5fe26ee3fa12

mmc: st: correct retries management

The retries number should be 3.
A warning message is added in mmc_block_read(), and the code is refactored.

Change-Id: I577c7dd91c451c7580b1660042cb5fe26ee3fa12
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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nand: raw_nand: fix timeout issue in nand_wait_ready

nand_wait_ready is called with a millisecond delay
but the timeout used a micro second. Fixing the conversion
in the timeout call.
The prototype

nand: raw_nand: fix timeout issue in nand_wait_ready

nand_wait_ready is called with a millisecond delay
but the timeout used a micro second. Fixing the conversion
in the timeout call.
The prototype of the function is also changed to use an unsigned int
parameter.

Change-Id: Ia3281be7980477dfbfdb842308d35ecd8b926fb8
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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mtd: spi_nor: change message level on macronix detection

Change the detection message from WARN to INFO when macronix
NOR is detected.

Change-Id: I488696f1fb75b823e85decfcd6cd32e7b36a6c2e
Signed-of

mtd: spi_nor: change message level on macronix detection

Change the detection message from WARN to INFO when macronix
NOR is detected.

Change-Id: I488696f1fb75b823e85decfcd6cd32e7b36a6c2e
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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gpio: stm32_gpio: check GPIO node status after checking DT

The call to fdt_get_status(node) has to be done after the DT is found
to be valid.

Fixes: 1fc2130c5 stm32mp1: update device tree and gpio

gpio: stm32_gpio: check GPIO node status after checking DT

The call to fdt_get_status(node) has to be done after the DT is found
to be valid.

Fixes: 1fc2130c5 stm32mp1: update device tree and gpio functions

Change-Id: I70f803aae3dde128a9e740f54c8837b64cb1a244
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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