tzc400: adjust filter flag if it is set to FILTER_BIT_ALL

TZC_400_REGION_ATTR_FILTER_BIT_ALL is a simple constant definition, so
it can't get the real filter number to construct the bit flag for all

tzc400: adjust filter flag if it is set to FILTER_BIT_ALL

TZC_400_REGION_ATTR_FILTER_BIT_ALL is a simple constant definition, so
it can't get the real filter number to construct the bit flag for all
existing filters. If the platform doesn't have 4 filters, passing
FILTER_BIT_ALL to tzc400_configure_region() will cause assertion or
misconfiguration. So adjust the bit flag against the real filter
number.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: Ie5c48303485f3b5015772961ee7c34746121ee84

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drivers/gicv3: also shift eSPI register offset in GICD_OFFSET_64()

ESPI register offset should also be shifted right by REG##R_SHIFT to
keep consistent.

It is not a functional issue, for GICD_OFFSE

drivers/gicv3: also shift eSPI register offset in GICD_OFFSET_64()

ESPI register offset should also be shifted right by REG##R_SHIFT to
keep consistent.

It is not a functional issue, for GICD_OFFSET_64() is only used for
GICD_IROUTER<E>, and IROUTER_SHIFT is 0.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I76eee5c50e4300890e78e80bddde135ce88daa2d

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drivers/gicv3: add debug log for maximum INTID of SPI and eSPI

Add debug log for the maximum supported INTID of SPI and eSPI on the
current GIC implementation.

Signed-off-by: Heyi Guo <guoheyi@linu

drivers/gicv3: add debug log for maximum INTID of SPI and eSPI

Add debug log for the maximum supported INTID of SPI and eSPI on the
current GIC implementation.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: Ie45ab1d85b39658c4ca4bc54ee433ac44e41d03f

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drivers/gicv3: limit SPI ID to avoid misjudgement in GICD_OFFSET()

The GICv3 architecture allows GICD_TYPER.ITLinesNumber to be 31, so
the maximum possible value for num_ints is 1024. The value must

drivers/gicv3: limit SPI ID to avoid misjudgement in GICD_OFFSET()

The GICv3 architecture allows GICD_TYPER.ITLinesNumber to be 31, so
the maximum possible value for num_ints is 1024. The value must be
limited to (MAX_SPI_ID + 1), or GICD_OFFSET() will consider it as ESPI
INTID and return wrong register address.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: Iddcb83d3e5d241b39f4176c19c2bceaa2c3dd653

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drivers/gicv3: fix logical issue for num_eints

In function gicv3_spis_config_defaults(), the variable num_ints is set
to (maximum SPI INTID + 1), while num_eints is set to (maximum ESPI
INTID). It i

drivers/gicv3: fix logical issue for num_eints

In function gicv3_spis_config_defaults(), the variable num_ints is set
to (maximum SPI INTID + 1), while num_eints is set to (maximum ESPI
INTID). It introduces not only inconsistency to the code, but also
logical bug in the "for" loops, for the INTID of num_eints is also
valid and the check should be inclusive.

Fix this by setting num_eints to (maximum ESPI INTID + 1) as well.

Fix similar issues in gicv3_distif_save() and
gicv3_distif_init_restore().

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I4425777d17e84e85f38853603340bd348640154f

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drivers/gicv3: fix potential GICD context override with ESPI enabled

RESTORE/SAVE_GICD_EREGS uses (int_id - (MIN_ESPI_ID - MIN_SPI_ID)) to
get the context array index for ESPI, which will override t

drivers/gicv3: fix potential GICD context override with ESPI enabled

RESTORE/SAVE_GICD_EREGS uses (int_id - (MIN_ESPI_ID - MIN_SPI_ID)) to
get the context array index for ESPI, which will override the space of
standard SPI starting from (MIN_SPI_ID + MIN_SPI_ID).

However, using TOTAL_SPI_INTR_NUM to replace the above MIN_SPI_ID
cannot totally fix the issue, for TOTAL_SPI_INTR_NUM is not well
aligned and the array index will be rounded down by the shifting
operation if being shifted more than 2 bits. It will cause buffer
override again when the existing maximum SPI reaches 1019.

So round up TOTAL_SPI_INTR_NUM with (1 << REG##R_SHIFT) for GICD
context arrays.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I5be2837c42f381a62f8d46a4ecd778009b1fe059

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drivers/gicv3: use mpidr to probe GICR for current CPU

In function gicv3_rdistif_probe(), line #1322 implies
gicv3_driver_data->mpidr_to_core_pos() may be null, but the original
code uses this inter

drivers/gicv3: use mpidr to probe GICR for current CPU

In function gicv3_rdistif_probe(), line #1322 implies
gicv3_driver_data->mpidr_to_core_pos() may be null, but the original
code uses this interface to get current CPU index unconditionally.

It is better to use MPIDR to probe GICR which does not depend on
gicv3_driver_data->mpidr_to_core_pos().

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I64add055385040fe0a56b977e2299608e2309a6e

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Merge changes from topic "scmi-msg" into integration

* changes:
doc: maintainers: add scmi server
drivers: move scmi-msg out of st

Merge changes Ic9bacaf3,I99a18dbb,I34803060,I3ed55aa4,Ic8eed072, ... into integration

* changes:
doc: renesas: Update RZ/G2 code owner list
plat: renesas: rzg: DT memory node enhancements
rene

Merge changes Ic9bacaf3,I99a18dbb,I34803060,I3ed55aa4,Ic8eed072, ... into integration

* changes:
doc: renesas: Update RZ/G2 code owner list
plat: renesas: rzg: DT memory node enhancements
renesas: rzg: emmc: Enable RZ/G2M support
plat: renesas: rzg: Add HopeRun HiHope RZ/G2M board support
drivers: renesas: rzg: Add HiHope RZ/G2M board support
tools: renesas: Add tool support for RZ/G2 platforms

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drivers: move scmi-msg out of st

Make the scmi-msg driver reused by others.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I5bc35fd4dab70f45c09b8aab65af4209cf23b124

marvell: uart: a3720: Fix macro name for 6th bit of Status Register

This patch does not change code, it only updates comments and macro name
for 6th bit of Status Register. So TF-A binary stay same.

marvell: uart: a3720: Fix macro name for 6th bit of Status Register

This patch does not change code, it only updates comments and macro name
for 6th bit of Status Register. So TF-A binary stay same.

6th bit of the Status Register is named TX EMPTY and is set to 1 when both
Transmitter Holding Register (THR) or Transmitter Shift Register (TSR) are
empty. It is when all characters were already transmitted.

There is also TX FIFO EMPTY bit in the Status Register which is set to 1
only when THR is empty.

In both console_a3700_core_init() and console_a3700_core_flush() functions
we should wait until both THR and TSR are empty therefore we should check
6th bit of the Status Register.

So current code is correct, just had misleading macro names and comments.
This change fixes this "documentation" issue, fixes macro name for 6th bit
of the Status Register and also updates comments.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I19e4e7f53a90bcfb318e6dd1b1249b6cbf81c4d3

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marvell: uart: a3720: Implement console_a3700_core_getc

Implementation is simple, just check if there is a pending character in
RX FIFO via RXRDY bit of Status Register and if yes, read it from
UART

marvell: uart: a3720: Implement console_a3700_core_getc

Implementation is simple, just check if there is a pending character in
RX FIFO via RXRDY bit of Status Register and if yes, read it from
UART_RX_REG register.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I226b6e336f44f5d0ca8dcb68e49a68e8f2f49708

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renesas: rzg: emmc: Enable RZ/G2M support

Enable eMMC driver support for RZ/G2M SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.ren

renesas: rzg: emmc: Enable RZ/G2M support

Enable eMMC driver support for RZ/G2M SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I34803060c5b592ac24720b11d4a8cd3f9f40caee

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renesas: rzg: Add PFC support for RZ/G2M

Add pin control support for RZ/G2M SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas

renesas: rzg: Add PFC support for RZ/G2M

Add pin control support for RZ/G2M SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I08719015cab1ec59e2270523980a0a3e26e72c01

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drivers: renesas: rzg: Add HiHope RZ/G2M board support

Add support for HiHope RZ/G2M board.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj

drivers: renesas: rzg: Add HiHope RZ/G2M board support

Add support for HiHope RZ/G2M board.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Ic8eed0729a42aeee94fc96d16b15b928232488a3

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renesas: rzg: Add QoS support for RZ/G2M

Add QoS support for RZ/G2M SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Ch

renesas: rzg: Add QoS support for RZ/G2M

Add QoS support for RZ/G2M SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: If541278fd629761cc83398bba71e63f09d9dbee6

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renesas: rzg: Add support for DRAM initialization

Add support for initializing DRAM on RZ/G2M SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev

renesas: rzg: Add support for DRAM initialization

Add support for initializing DRAM on RZ/G2M SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I99f1a6971a061a44687af498d55306a93e4fc8f7

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drivers: renesas: Move ddr/qos/qos header files

Move DDR/QoS/PFC header files, so that the same code
can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz@bp.r

drivers: renesas: Move ddr/qos/qos header files

Move DDR/QoS/PFC header files, so that the same code
can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I2cc0ceda8d05b6b8d95a69afdc233dc0d098e850

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drivers: renesas: rpc: Move to common

Move rpc driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz@bp.

drivers: renesas: rpc: Move to common

Move rpc driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I04805d720d95b8edcc14e652f897fadc7f432197

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drivers: renesas: avs: Move to common

Move avs driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz@bp.

drivers: renesas: avs: Move to common

Move avs driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I85d9fa8b6abf158ce2521f1696478f7c5339fc42

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drivers: renesas: auth: Move to common

Move authentication driver code to common directory, so that the
same code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <bij

drivers: renesas: auth: Move to common

Move authentication driver code to common directory, so that the
same code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I02592dfc714998bf89b9feaa78f685ae36be6f59

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drivers: renesas: dma: Move to common

Move dma driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz@bp.

drivers: renesas: dma: Move to common

Move dma driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Idce2e2f4e098cfc17219f963373d20ebf74e5b7c

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drivers: renesas: watchdog: Move to common

Move watch driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das

drivers: renesas: watchdog: Move to common

Move watch driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I235f2cde325a0feeadbfc4b7ee02e8b1186f7ea1

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drivers: renesas: rom: Move to common

Move rom driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz@bp.

drivers: renesas: rom: Move to common

Move rom driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I399dfb5eff186db76d26fa9c54bea88bee66789c

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drivers: renesas: delay: Move to common

Move delay driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz

drivers: renesas: delay: Move to common

Move delay driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I5e806bd0e0a0a4b436048513b7089db90ff9805f

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