Merge changes from topic "a3700-comphy-fixes-1" into integration

* changes:
refactor(drivers/marvell/comphy-3700): rename Clock Source Low value constants
refactor(drivers/marvell/comphy-3700):

Merge changes from topic "a3700-comphy-fixes-1" into integration

* changes:
refactor(drivers/marvell/comphy-3700): rename Clock Source Low value constants
refactor(drivers/marvell/comphy-3700): rename Clock Source Low register constants
refactor(drivers/marvell/comphy-3700): rename Reset and Clock Control register constants
refactor(drivers/marvell/comphy-3700): rename Lane Status 1 register constants
refactor(drivers/marvell/comphy-3700): rename Miscellaneous Control register constants
refactor(drivers/marvell/comphy-3700): rename Idle Sync Enable register constants
refactor(drivers/marvell/comphy-3700): unify Generation Settings register values
refactor(drivers/marvell/comphy-3700): unify Generation Settings register names
refactor(drivers/marvell/comphy-3700): drop _ADDR suffixes
refactor(drivers/marvell/comphy-3700): drop _REG prefixes and suffixes
refactor(drivers/marvell/comphy-3700): move and add comment for COMPHY_RESERVED_REG
refactor(drivers/marvell/comphy-3700): move Miscellaneous Control 0 register definition
refactor(drivers/marvell/comphy-3700): rename PHY_GEN_USB3_5G to PHY_GEN_MAX_USB3_5G
refactor(drivers/marvell/comphy-3700): rename Digital Loopback Enable register constant
fix(drivers/marvell/comphy): change reg_set() / reg_set16() to update semantics
fix(drivers/marvell/comphy-3700): use reg_set() according to update semantics
fix(drivers/marvell/comphy-3700): fix comments about selector register values
fix(drivers/marvell/comphy-3700): fix comment about COMPHY status register
fix(drivers/marvell/comphy-3700): fix reference clock selection value names
fix(drivers/marvell/comphy-3700): drop MODE_REFDIV constant
fix(drivers/marvell/comphy-3700): fix SerDes frequency register value name
fix(drivers/marvell/comphy-3700): fix Generation Setting registers names
fix(drivers/marvell/comphy-3700): fix PIN_PU_IVREF register name

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refactor(drivers/marvell/comphy-3700): rename Clock Source Low value constants

The constants BUNDLE_PERIOD_SCALE and PLL_READY_DLY refer to two
multi-bit registers within the Clock Source Low regist

refactor(drivers/marvell/comphy-3700): rename Clock Source Low value constants

The constants BUNDLE_PERIOD_SCALE and PLL_READY_DLY refer to two
multi-bit registers within the Clock Source Low register. These
constants are used as masks for those registers (and values are not
defined since we are writing zeros to them).

Give them the _MASK suffix.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Id469d0ab4c755d2d6a0150a1ade33dd9d0293667

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refactor(drivers/marvell/comphy-3700): rename Clock Source Low register constants

The register at offset 0x1C3 is called Clock Source Low in functional
specification, but we use constant name GLOB_C

refactor(drivers/marvell/comphy-3700): rename Clock Source Low register constants

The register at offset 0x1C3 is called Clock Source Low in functional
specification, but we use constant name GLOB_CLK_SRC_LO. Rename it to
RST_CLK_CTRL instead.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: If7ca460cb166f3828678e1e09c4e6caf5bb77770

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refactor(drivers/marvell/comphy-3700): rename Reset and Clock Control register constants

The register at offset 0x1C1 is called Reset and Clock Control in
functional specification, but we use consta

refactor(drivers/marvell/comphy-3700): rename Reset and Clock Control register constants

The register at offset 0x1C1 is called Reset and Clock Control in
functional specification, but we use constant name GLOB_PHY_CTRL0.
Rename it to RST_CLK_CTRL instead.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I5dac8913bd0686d4f5bd74b91cb7d07ba06df72b

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refactor(drivers/marvell/comphy-3700): rename Lane Status 1 register constants

Rename the Lane Status 1 register constants from LANE_STATUS1 to
LANE_STAT1, to use an abbreviation similar to that for

refactor(drivers/marvell/comphy-3700): rename Lane Status 1 register constants

Rename the Lane Status 1 register constants from LANE_STATUS1 to
LANE_STAT1, to use an abbreviation similar to that for Lane
Configuration registers (where we use LANE_CFGx instead of LANE_CONFIGx
or LANE_CONFIGURATIONx).

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ie329d5a93615efe261802a2f027475b602a5c840

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refactor(drivers/marvell/comphy-3700): rename Miscellaneous Control register constants

Rename the Miscellaneous Control register constants from MISC_REGx to
MISC_CTRLx.

Signed-off-by: Marek Behún <

refactor(drivers/marvell/comphy-3700): rename Miscellaneous Control register constants

Rename the Miscellaneous Control register constants from MISC_REGx to
MISC_CTRLx.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I4d43bbda44b090de4ecf2d52cfc468f9683cc3b5

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refactor(drivers/marvell/comphy-3700): rename Idle Sync Enable register constants

According to the functional specification, the register at offset 0x48
is called Idle Sync Enable, not Unit Control

refactor(drivers/marvell/comphy-3700): rename Idle Sync Enable register constants

According to the functional specification, the register at offset 0x48
is called Idle Sync Enable, not Unit Control or some such.

Rename the constants.

Only bit 12 of this register is defined, all other bits are reserved.
But for some reason the code needs the default value of the other bits,
so we also rename constant UNIT_CTRL_DEFAULT_VALUE to
IDLE_SYNC_EN_DEFAULT_VALUE.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ia4f80f945a8f31c190cd9a1875d50d892e72825f

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refactor(drivers/marvell/comphy-3700): unify Generation Settings register values

Generation Settings registers have the same layout for different
generations and same setting (i.e. Generation 2 Sett

refactor(drivers/marvell/comphy-3700): unify Generation Settings register values

Generation Settings registers have the same layout for different
generations and same setting (i.e. Generation 2 Settings 2 register has
the same layout as Generation 3 Settings 2).

So it does not make sense to prefix the constants for Settings 2 with
G3.

Instead change the prefixes to GSx_ for settings register x.

For Settings 2 of Gen 2 and Gen 3 we have some definitions in the first
and some in the second. Move them all to the first defined register (in
this case Gen 2, since the constant for Gen 1 is not defined because it
is not used).

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I15c337eb58aa37fd99fe388fd59373aa325a3a92

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refactor(drivers/marvell/comphy-3700): unify Generation Settings register names

Sometimes we call the constants GENx_SET_y, sometimes GENx_SETTINGS_y,
and sometimes GENx_SETTING_y.

Unify this into

refactor(drivers/marvell/comphy-3700): unify Generation Settings register names

Sometimes we call the constants GENx_SET_y, sometimes GENx_SETTINGS_y,
and sometimes GENx_SETTING_y.

Unify this into GENx_SETy.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I3810fb52b2897fe6730ef6e58d434c47cfef14a9

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refactor(drivers/marvell/comphy-3700): drop _ADDR suffixes

COMPHY register addresses are defined twice
- once for indirect access, where the constants are of the form
COMPHY_<register_name>
- once

refactor(drivers/marvell/comphy-3700): drop _ADDR suffixes

COMPHY register addresses are defined twice
- once for indirect access, where the constants are of the form
COMPHY_<register_name>
- once for direct access, with constants of the form
<register_name>_ADDR

But sometimes the first case also has this _ADDR suffix (and other times
not).

Drop it from those places to unify how we define these registers.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ibf95be8ade231d0e42258f40614a5f0974d280bd

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refactor(drivers/marvell/comphy-3700): drop _REG prefixes and suffixes

Some register constants are defined with _REG suffix or REG_ prefix, but
others are not. Unify this by dropping these prefixes

refactor(drivers/marvell/comphy-3700): drop _REG prefixes and suffixes

Some register constants are defined with _REG suffix or REG_ prefix, but
others are not. Unify this by dropping these prefixes / suffixes.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I1ba331c0a4686093ee250bcaf3297349956ac9a8

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refactor(drivers/marvell/comphy-3700): move and add comment for COMPHY_RESERVED_REG

The COMPHY_RESERVED_REG (offset 0x0E) is currently defined between
COMPHY_KVCO_CAL_CTRL (0x02) and COMPHY_DIG_LOOP

refactor(drivers/marvell/comphy-3700): move and add comment for COMPHY_RESERVED_REG

The COMPHY_RESERVED_REG (offset 0x0E) is currently defined between
COMPHY_KVCO_CAL_CTRL (0x02) and COMPHY_DIG_LOOPBACK_EN (0x23).

But this register does not come from PHY lane register space. The
address 0x0E is not relative to PHY lane registers base address.

It only exists in the indirect register space, before PHY lane 2
registers (which start at address 0x200).

Move its definition in the header and add a comment.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ie726384b980ace83d8ea327df09d928db74c2ab7

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refactor(drivers/marvell/comphy-3700): move Miscellaneous Control 0 register definition

Move the definitions for the Miscellaneous Control 0 register (offset 0x4F),
to leave the registers sorted acc

refactor(drivers/marvell/comphy-3700): move Miscellaneous Control 0 register definition

Move the definitions for the Miscellaneous Control 0 register (offset 0x4F),
to leave the registers sorted according to their offsets.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I9864be5bd00181d21c9334219be4f89c4f032c8b

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refactor(drivers/marvell/comphy-3700): rename PHY_GEN_USB3_5G to PHY_GEN_MAX_USB3_5G

The register name for the value PHY_GEN_USB3_5G is PHY_GEN_MAX. We
already define the mask constant as PHY_GEN_MA

refactor(drivers/marvell/comphy-3700): rename PHY_GEN_USB3_5G to PHY_GEN_MAX_USB3_5G

The register name for the value PHY_GEN_USB3_5G is PHY_GEN_MAX. We
already define the mask constant as PHY_GEN_MAX_MASK. Thus also the
value name should be prefixed with PHY_GEN_MAX_.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ibf72a66d2e65e240ed2cdbc3a301dbd793e2cb34

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refactor(drivers/marvell/comphy-3700): rename Digital Loopback Enable register constant

The register at offset 0x23 is called Digital Loopback Enable, but the
constant is COMPHY_LOOPBACK_REG0, as if

refactor(drivers/marvell/comphy-3700): rename Digital Loopback Enable register constant

The register at offset 0x23 is called Digital Loopback Enable, but the
constant is COMPHY_LOOPBACK_REG0, as if there were some LOOPBACK_REG1
register or something, which there is not.

Rename the constant to COMPHY_DIG_LOOPBACK_EN.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ie88bdd864e2c9ab7e8de70ed7f3a13ee8f08ff79

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fix(drivers/marvell/comphy-3700): fix comments about selector register values

The comments about selector register values are wrong.

Bit 0 configures only lane 1, bit 4 only lane 0, and bit 8 lanes

fix(drivers/marvell/comphy-3700): fix comments about selector register values

The comments about selector register values are wrong.

Bit 0 configures only lane 1, bit 4 only lane 0, and bit 8 lanes 0 and
2.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Iffe42374f92654ebe570557e0d462204439cfa31

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fix(drivers/marvell/comphy-3700): fix comment about COMPHY status register

Fix comment about COMPHY status register. PCIe/GbE0 PHY is on lane 1,
while USB3/GbE1 on lane 0.

Signed-off-by: Marek Behú

fix(drivers/marvell/comphy-3700): fix comment about COMPHY status register

Fix comment about COMPHY status register. PCIe/GbE0 PHY is on lane 1,
while USB3/GbE1 on lane 0.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I24734a61727d56f6eab2ed1c366d7a1810dbe19d

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fix(drivers/marvell/comphy-3700): fix reference clock selection value names

The current definitions of reference clock speed register values
#define PCIE_REF_CLOCK_SPEED_25M REF_CLOCK_SPEED_

fix(drivers/marvell/comphy-3700): fix reference clock selection value names

The current definitions of reference clock speed register values
#define PCIE_REF_CLOCK_SPEED_25M REF_CLOCK_SPEED_30M
#define USB3_REF_CLOCK_SPEED_25M REF_CLOCK_SPEED_30M
is ambiguous. The name of the constant implies 25 MHz, but the value
implies 30 MHz, which may make the reader think that the setting has
something to do with both values.

In reality, the values have different tables for SerDes and PCIe/USB3
PHY mode. The value for 25 MHz for PCIe/USB3 mode (0x2) is the value
for 30 MHz for SerDes mode.

Instead of defining the PCIe/USB3 constants relative to SerDes
constants, define them with absolute values, thus making it a little bit
more obvious that different modes have different value tables.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I50c66c6bbe22b9a9bec4685600cb8560524a643c

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fix(drivers/marvell/comphy-3700): drop MODE_REFDIV constant

The MODE_REFDIV constant is only used as mask of the MODE_REFDIV
register, but we already have MODE_REFDIV_MASK constant for that.

Drop M

fix(drivers/marvell/comphy-3700): drop MODE_REFDIV constant

The MODE_REFDIV constant is only used as mask of the MODE_REFDIV
register, but we already have MODE_REFDIV_MASK constant for that.

Drop MODE_REFDIV.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Icabb32189a7ca1a857dcf86cf0846bd0335f75d0

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fix(drivers/marvell/comphy-3700): fix SerDes frequency register value name

Constants SD_SPEED_1_25_G and SD_SPEED_2_5_G refer to SerDes frequency,
which is 1.25x that of data rate, since 1000base-x

fix(drivers/marvell/comphy-3700): fix SerDes frequency register value name

Constants SD_SPEED_1_25_G and SD_SPEED_2_5_G refer to SerDes frequency,
which is 1.25x that of data rate, since 1000base-x and 2500base-x use
the 8b/10b encoding:

mode frequency data rate
1000base-x 1.25 GHz 1 Gbps
2500base-x 3.125 GHz 2.5 Gbps

But the first constant refers to the frequency, while the second to the
data rate, which does not make sense.

Since the values in the specification refer to frequency, change the
name of the constant SD_SPEED_2_5_G to SD_SPEED_3_125_G to also refer to
the frequency, as SD_SPEED_1_25_G does.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I7670b45fa685aff93b3cafd84cf30d93620d8da1

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fix(drivers/marvell/comphy-3700): fix Generation Setting registers names

According to Functional Specification, the common PHY register at offset
0x3f is actually Generation 3 Setting 2, while the r

fix(drivers/marvell/comphy-3700): fix Generation Setting registers names

According to Functional Specification, the common PHY register at offset
0x3f is actually Generation 3 Setting 2, while the register at offset
0x112 is Generation 2 Setting 3.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I4626672cbee2d08da1da7839a3cf3f90e78fa101

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fix(drivers/marvell/comphy-3700): fix PIN_PU_IVREF register name

According to Functional Specification, the register at bit 1 of PHY
Configuration 1 is called PIN_PU_IVREF, not PIN_PU_IVEREF. Fix th

fix(drivers/marvell/comphy-3700): fix PIN_PU_IVREF register name

According to Functional Specification, the register at bit 1 of PHY
Configuration 1 is called PIN_PU_IVREF, not PIN_PU_IVEREF. Fix this.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I912fa4a1956bf0b1b35a24925db03e3dbbe1adf3

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Merge changes Id2a538c3,Ifa0339e7,I8b09fab8 into integration

* changes:
drivers: marvell: comphy-a3700: Set TXDCLK_2X_SEL bit during PCIe initialization
drivers: marvell: comphy-a3700: Set mask

Merge changes Id2a538c3,Ifa0339e7,I8b09fab8 into integration

* changes:
drivers: marvell: comphy-a3700: Set TXDCLK_2X_SEL bit during PCIe initialization
drivers: marvell: comphy-a3700: Set mask parameter for every reg_set call
drivers: marvell: comphy-a3700: Fix configuring polarity invert bits

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drivers: marvell: comphy-a3700: Set TXDCLK_2X_SEL bit during PCIe initialization

Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link
Initialization says that TXDCLK_2X_SEL bit need

drivers: marvell: comphy-a3700: Set TXDCLK_2X_SEL bit during PCIe initialization

Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link
Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe
Root Complex mode. Both U-Boot and Linux kernel support only Root Complex
mode. Set this bit.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Id2a538c379b911b62597f9463b4842b7b5c24df7

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Merge pull request #1673 from antonio-nino-diaz-arm/an/headers

Standardise header guards across codebase