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65d68ca6 |
| 04-Aug-2016 |
Sudeep Holla <sudeep.holla@arm.com> |
gicv3: disable Group1 NonSecure interrupts during core powerdown
As per the GICv3 specification, to power down a processor using GICv3 and allow automatic power-on if an interrupt must be sent to a
gicv3: disable Group1 NonSecure interrupts during core powerdown
As per the GICv3 specification, to power down a processor using GICv3 and allow automatic power-on if an interrupt must be sent to a processor, software must set Enable to zero for all interrupt groups(by writing to GICC_CTLR or ICC_IGRPEN{0,1}_EL1/3 as appropriate.
Also, NonSecure EL1 software may not be aware of the CPU power state details and fail to choose right states that require quiescing the CPU interface. So it's preferred that the PSCI implementation handles it as it is fully aware of the CPU power states.
This patch adds disabling of Group1 NonSecure interrupts during processor power down along with Group0 and Group1 Secure interrupts so that all the interrupt groups are handled at once as per specification.
Change-Id: Ib564d773c9c4c41f2ca9471451c030e3de75e641
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367d0ffb |
| 05-May-2016 |
Soby Mathew <soby.mathew@arm.com> |
AArch32: Enable GIC and TZC support
This patch modifies GICv3 and TZC drivers to add AArch32 support. No modifications are required for the GICv2 driver for AArch32 support. The TZC driver assumes t
AArch32: Enable GIC and TZC support
This patch modifies GICv3 and TZC drivers to add AArch32 support. No modifications are required for the GICv2 driver for AArch32 support. The TZC driver assumes that the secure world is running in Little-Endian mode to do 64 bit manipulations. Assertions are present to validate the assumption.
Note: The legacy GICv3 driver is not supported for AArch32.
Change-Id: Id1bc75a9f5dafb9715c9500ca77b4606eb1e2458
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4a966306 |
| 11-Feb-2016 |
danh-arm <dan.handley@arm.com> |
Merge pull request #517 from soby-mathew/sm/gic_set_prio_fix
Fix IPRIORITY and ITARGET accessors in GIC drivers
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e9ec3cec |
| 01-Feb-2016 |
Soby Mathew <soby.mathew@arm.com> |
Move private APIs in gic_common.h to a private header
This patch moves the private GIC common accessors from `gic_common.h` to a new private header file `gic_common_private.h`. This patch also adds
Move private APIs in gic_common.h to a private header
This patch moves the private GIC common accessors from `gic_common.h` to a new private header file `gic_common_private.h`. This patch also adds additional comments to GIC register accessors to highlight the fact that some of them access register values that correspond to multiple interrupt IDs. The convention used is that the `set`, `get` and `clr` accessors access and modify the values corresponding to a single interrupt ID whereas the `read` and `write` GIC register accessors access the raw GIC registers and it could correspond to multiple interrupt IDs depending on the register accessed.
Change-Id: I2643ecb2533f01e3d3219fcedfb5f80c120622f9
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4ca473db |
| 09-Dec-2015 |
danh-arm <dan.handley@arm.com> |
Merge pull request #456 from soby-mathew/sm/gicv3-tsp-plat-changes-v2
Modify TSP and ARM standard platforms for new GIC drivers v2
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03ffb6bd |
| 03-Dec-2015 |
Soby Mathew <soby.mathew@arm.com> |
Rename GICv3 interrupt group macros
This patch renames the GICv3 interrupt group macros from INT_TYPE_G0, INT_TYPE_G1S and INT_TYPE_G1NS to INTR_GROUP0, INTR_GROUP1S and INTR_GROUP1NS respectively.
Rename GICv3 interrupt group macros
This patch renames the GICv3 interrupt group macros from INT_TYPE_G0, INT_TYPE_G1S and INT_TYPE_G1NS to INTR_GROUP0, INTR_GROUP1S and INTR_GROUP1NS respectively.
Change-Id: I40c66f589ce6234fa42205adcd91f7d6ad8f33d4
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b39908af |
| 26-Nov-2015 |
Achin Gupta <achin.gupta@arm.com> |
Merge pull request #439 from soby-mathew/sm/new-gic-driver
Introduce new GICv3 and GICv2 drivers
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df373737 |
| 03-Sep-2015 |
Achin Gupta <achin.gupta@arm.com> |
Add ARM GICv3 driver without support for legacy operation
This patch adds a driver for ARM GICv3 systems that need to run software stacks where affinity routing is enabled across all privileged exce
Add ARM GICv3 driver without support for legacy operation
This patch adds a driver for ARM GICv3 systems that need to run software stacks where affinity routing is enabled across all privileged exception levels for both security states. This driver is a partial implementation of the ARM Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069A). The driver does not cater for legacy support of interrupts and asymmetric configurations.
The existing GIC driver has been preserved unchanged. The common code for GICv2 and GICv3 systems has been refactored into a new file, `drivers/arm/gic/common/gic_common.c`. The corresponding header is in `include/drivers/arm/gic_common.h`.
The driver interface is implemented in `drivers/arm/gic/v3/gicv3_main.c`. The corresponding header is in `include/drivers/arm/gicv3.h`. Helper functions are implemented in `drivers/arm/gic/v3/arm_gicv3_helpers.c` and are accessible through the `drivers/arm/gic/v3/gicv3_private.h` header.
Change-Id: I8c3c834a1d049d05b776b4dcb76b18ccb927444a
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