1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <debug.h> 35 #include <gic_common.h> 36 #include <gicv3.h> 37 #include "../common/gic_common_private.h" 38 #include "gicv3_private.h" 39 40 static const gicv3_driver_data_t *driver_data; 41 static unsigned int gicv2_compat; 42 43 /******************************************************************************* 44 * This function initialises the ARM GICv3 driver in EL3 with provided platform 45 * inputs. 46 ******************************************************************************/ 47 void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) 48 { 49 unsigned int gic_version; 50 51 assert(plat_driver_data); 52 assert(plat_driver_data->gicd_base); 53 assert(plat_driver_data->gicr_base); 54 assert(plat_driver_data->rdistif_num); 55 assert(plat_driver_data->rdistif_base_addrs); 56 57 assert(IS_IN_EL3()); 58 59 /* 60 * The platform should provide a list of at least one type of 61 * interrupts 62 */ 63 assert(plat_driver_data->g0_interrupt_array || 64 plat_driver_data->g1s_interrupt_array); 65 66 /* 67 * If there are no interrupts of a particular type, then the number of 68 * interrupts of that type should be 0 and vice-versa. 69 */ 70 assert(plat_driver_data->g0_interrupt_array ? 71 plat_driver_data->g0_interrupt_num : 72 plat_driver_data->g0_interrupt_num == 0); 73 assert(plat_driver_data->g1s_interrupt_array ? 74 plat_driver_data->g1s_interrupt_num : 75 plat_driver_data->g1s_interrupt_num == 0); 76 77 /* Check for system register support */ 78 assert(read_id_aa64pfr0_el1() & 79 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)); 80 81 /* The GIC version should be 3.0 */ 82 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 83 gic_version >>= PIDR2_ARCH_REV_SHIFT; 84 gic_version &= PIDR2_ARCH_REV_MASK; 85 assert(gic_version == ARCH_REV_GICV3); 86 87 /* 88 * Find out whether the GIC supports the GICv2 compatibility mode. The 89 * ARE_S bit resets to 0 if supported 90 */ 91 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); 92 gicv2_compat >>= CTLR_ARE_S_SHIFT; 93 gicv2_compat = !(gicv2_compat & CTLR_ARE_S_MASK); 94 95 /* 96 * Find the base address of each implemented Redistributor interface. 97 * The number of interfaces should be equal to the number of CPUs in the 98 * system. The memory for saving these addresses has to be allocated by 99 * the platform port 100 */ 101 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, 102 plat_driver_data->rdistif_num, 103 plat_driver_data->gicr_base, 104 plat_driver_data->mpidr_to_core_pos); 105 106 driver_data = plat_driver_data; 107 108 INFO("GICv3 %s legacy support detected." 109 " ARM GICV3 driver initialized in EL3\n", 110 gicv2_compat ? "with" : "without"); 111 } 112 113 /******************************************************************************* 114 * This function initialises the GIC distributor interface based upon the data 115 * provided by the platform while initialising the driver. 116 ******************************************************************************/ 117 void gicv3_distif_init(void) 118 { 119 assert(driver_data); 120 assert(driver_data->gicd_base); 121 assert(driver_data->g1s_interrupt_array); 122 assert(driver_data->g0_interrupt_array); 123 124 assert(IS_IN_EL3()); 125 126 /* 127 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 128 * the ARE_S bit. The Distributor might generate a system error 129 * otherwise. 130 */ 131 gicd_clr_ctlr(driver_data->gicd_base, 132 CTLR_ENABLE_G0_BIT | 133 CTLR_ENABLE_G1S_BIT | 134 CTLR_ENABLE_G1NS_BIT, 135 RWP_TRUE); 136 137 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 138 gicd_set_ctlr(driver_data->gicd_base, 139 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 140 141 /* Set the default attribute of all SPIs */ 142 gicv3_spis_configure_defaults(driver_data->gicd_base); 143 144 /* Configure the G1S SPIs */ 145 gicv3_secure_spis_configure(driver_data->gicd_base, 146 driver_data->g1s_interrupt_num, 147 driver_data->g1s_interrupt_array, 148 INTR_GROUP1S); 149 150 /* Configure the G0 SPIs */ 151 gicv3_secure_spis_configure(driver_data->gicd_base, 152 driver_data->g0_interrupt_num, 153 driver_data->g0_interrupt_array, 154 INTR_GROUP0); 155 156 /* Enable the secure SPIs now that they have been configured */ 157 gicd_set_ctlr(driver_data->gicd_base, 158 CTLR_ENABLE_G1S_BIT | CTLR_ENABLE_G0_BIT, 159 RWP_TRUE); 160 } 161 162 /******************************************************************************* 163 * This function initialises the GIC Redistributor interface of the calling CPU 164 * (identified by the 'proc_num' parameter) based upon the data provided by the 165 * platform while initialising the driver. 166 ******************************************************************************/ 167 void gicv3_rdistif_init(unsigned int proc_num) 168 { 169 uintptr_t gicr_base; 170 171 assert(driver_data); 172 assert(proc_num < driver_data->rdistif_num); 173 assert(driver_data->rdistif_base_addrs); 174 assert(driver_data->gicd_base); 175 assert(gicd_read_ctlr(driver_data->gicd_base) & CTLR_ARE_S_BIT); 176 assert(driver_data->g1s_interrupt_array); 177 assert(driver_data->g0_interrupt_array); 178 179 assert(IS_IN_EL3()); 180 181 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 182 183 /* Set the default attribute of all SGIs and PPIs */ 184 gicv3_ppi_sgi_configure_defaults(gicr_base); 185 186 /* Configure the G1S SGIs/PPIs */ 187 gicv3_secure_ppi_sgi_configure(gicr_base, 188 driver_data->g1s_interrupt_num, 189 driver_data->g1s_interrupt_array, 190 INTR_GROUP1S); 191 192 /* Configure the G0 SGIs/PPIs */ 193 gicv3_secure_ppi_sgi_configure(gicr_base, 194 driver_data->g0_interrupt_num, 195 driver_data->g0_interrupt_array, 196 INTR_GROUP0); 197 } 198 199 /******************************************************************************* 200 * This function enables the GIC CPU interface of the calling CPU using only 201 * system register accesses. 202 ******************************************************************************/ 203 void gicv3_cpuif_enable(unsigned int proc_num) 204 { 205 uintptr_t gicr_base; 206 unsigned int scr_el3; 207 unsigned int icc_sre_el3; 208 209 assert(driver_data); 210 assert(proc_num < driver_data->rdistif_num); 211 assert(driver_data->rdistif_base_addrs); 212 assert(IS_IN_EL3()); 213 214 /* Mark the connected core as awake */ 215 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 216 gicv3_rdistif_mark_core_awake(gicr_base); 217 218 /* Disable the legacy interrupt bypass */ 219 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT; 220 221 /* 222 * Enable system register access for EL3 and allow lower exception 223 * levels to configure the same for themselves. If the legacy mode is 224 * not supported, the SRE bit is RAO/WI 225 */ 226 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 227 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); 228 229 scr_el3 = read_scr_el3(); 230 231 /* 232 * Switch to NS state to write Non secure ICC_SRE_EL1 and 233 * ICC_SRE_EL2 registers. 234 */ 235 write_scr_el3(scr_el3 | SCR_NS_BIT); 236 isb(); 237 238 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3); 239 write_icc_sre_el1(ICC_SRE_SRE_BIT); 240 isb(); 241 242 /* Switch to secure state. */ 243 write_scr_el3(scr_el3 & (~SCR_NS_BIT)); 244 isb(); 245 246 /* Program the idle priority in the PMR */ 247 write_icc_pmr_el1(GIC_PRI_MASK); 248 249 /* Enable Group0 interrupts */ 250 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT); 251 252 /* Enable Group1 Secure interrupts */ 253 write_icc_igrpen1_el3(read_icc_igrpen1_el3() | 254 IGRPEN1_EL3_ENABLE_G1S_BIT); 255 256 /* Write the secure ICC_SRE_EL1 register */ 257 write_icc_sre_el1(ICC_SRE_SRE_BIT); 258 isb(); 259 } 260 261 /******************************************************************************* 262 * This function disables the GIC CPU interface of the calling CPU using 263 * only system register accesses. 264 ******************************************************************************/ 265 void gicv3_cpuif_disable(unsigned int proc_num) 266 { 267 uintptr_t gicr_base; 268 269 assert(driver_data); 270 assert(proc_num < driver_data->rdistif_num); 271 assert(driver_data->rdistif_base_addrs); 272 273 assert(IS_IN_EL3()); 274 275 /* Disable legacy interrupt bypass */ 276 write_icc_sre_el3(read_icc_sre_el3() | 277 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)); 278 279 /* Disable Group0 interrupts */ 280 write_icc_igrpen0_el1(read_icc_igrpen0_el1() & 281 ~IGRPEN1_EL1_ENABLE_G0_BIT); 282 283 /* Disable Group1 Secure and Non-Secure interrupts */ 284 write_icc_igrpen1_el3(read_icc_igrpen1_el3() & 285 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT | 286 IGRPEN1_EL3_ENABLE_G1S_BIT)); 287 288 /* Synchronise accesses to group enable registers */ 289 isb(); 290 291 /* Mark the connected core as asleep */ 292 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 293 gicv3_rdistif_mark_core_asleep(gicr_base); 294 } 295 296 /******************************************************************************* 297 * This function returns the id of the highest priority pending interrupt at 298 * the GIC cpu interface. 299 ******************************************************************************/ 300 unsigned int gicv3_get_pending_interrupt_id(void) 301 { 302 unsigned int id; 303 304 assert(IS_IN_EL3()); 305 id = read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 306 307 /* 308 * If the ID is special identifier corresponding to G1S or G1NS 309 * interrupt, then read the highest pending group 1 interrupt. 310 */ 311 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) 312 return read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; 313 314 return id; 315 } 316 317 /******************************************************************************* 318 * This function returns the type of the highest priority pending interrupt at 319 * the GIC cpu interface. The return values can be one of the following : 320 * PENDING_G1S_INTID : The interrupt type is secure Group 1. 321 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1. 322 * 0 - 1019 : The interrupt type is secure Group 0. 323 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 324 * sufficient priority to be signaled 325 ******************************************************************************/ 326 unsigned int gicv3_get_pending_interrupt_type(void) 327 { 328 assert(IS_IN_EL3()); 329 return read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 330 } 331 332 /******************************************************************************* 333 * This function returns the type of the interrupt id depending upon the group 334 * this interrupt has been configured under by the interrupt controller i.e. 335 * group0 or group1 Secure / Non Secure. The return value can be one of the 336 * following : 337 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt 338 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt 339 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure 340 * interrupt. 341 ******************************************************************************/ 342 unsigned int gicv3_get_interrupt_type(unsigned int id, 343 unsigned int proc_num) 344 { 345 unsigned int igroup, grpmodr; 346 uintptr_t gicr_base; 347 348 assert(IS_IN_EL3()); 349 assert(driver_data); 350 351 /* Ensure the parameters are valid */ 352 assert(id < PENDING_G1S_INTID || id >= MIN_LPI_ID); 353 assert(proc_num < driver_data->rdistif_num); 354 355 /* All LPI interrupts are Group 1 non secure */ 356 if (id >= MIN_LPI_ID) 357 return INTR_GROUP1NS; 358 359 if (id < MIN_SPI_ID) { 360 assert(driver_data->rdistif_base_addrs); 361 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 362 igroup = gicr_get_igroupr0(gicr_base, id); 363 grpmodr = gicr_get_igrpmodr0(gicr_base, id); 364 } else { 365 assert(driver_data->gicd_base); 366 igroup = gicd_get_igroupr(driver_data->gicd_base, id); 367 grpmodr = gicd_get_igrpmodr(driver_data->gicd_base, id); 368 } 369 370 /* 371 * If the IGROUP bit is set, then it is a Group 1 Non secure 372 * interrupt 373 */ 374 if (igroup) 375 return INTR_GROUP1NS; 376 377 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */ 378 if (grpmodr) 379 return INTR_GROUP1S; 380 381 /* Else it is a Group 0 Secure interrupt */ 382 return INTR_GROUP0; 383 } 384