| d4486391 | 18-May-2016 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Add 32 bit version of plat_get_syscnt_freq
Added plat_get_syscnt_freq2, which is a 32 bit variant of the 64 bit
plat_get_syscnt_freq. The old one has been flagged as deprecated.
Common code has been
Add 32 bit version of plat_get_syscnt_freq
Added plat_get_syscnt_freq2, which is a 32 bit variant of the 64 bit
plat_get_syscnt_freq. The old one has been flagged as deprecated.
Common code has been updated to use this new version. Porting guide
has been updated.
Change-Id: I9e913544926c418970972bfe7d81ee88b4da837e
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|
| fa7d172b | 04-May-2016 |
danh-arm <dan.handley@arm.com> |
Merge pull request #614 from soby-mathew/sm/rem_fvp_ve_memmap
FVP: Remove VE memory map support and change default GIC driver |
| a8af6a4d | 07-Apr-2016 |
Soby Mathew <soby.mathew@arm.com> |
Change the default driver to GICv3 in FVP
This patch changes the default driver for FVP platform from the deprecated
GICv3 legacy to the GICv3 only driver. This means that the default build of
Trust
Change the default driver to GICv3 in FVP
This patch changes the default driver for FVP platform from the deprecated
GICv3 legacy to the GICv3 only driver. This means that the default build of
Trusted Firmware will not be able boot Linux kernel with GICv2 FDT blob. The
user guide is also updated to reflect this change of default GIC driver for
FVP.
Change-Id: Id6fc8c1ac16ad633dabb3cd189b690415a047764
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|
| 21a3973d | 13-Jan-2016 |
Soby Mathew <soby.mathew@arm.com> |
Remove support for legacy VE memory map in FVP
This patch removes support for legacy Versatile Express memory map for the
GIC peripheral in the FVP platform. The user guide is also updated for the
s
Remove support for legacy VE memory map in FVP
This patch removes support for legacy Versatile Express memory map for the
GIC peripheral in the FVP platform. The user guide is also updated for the
same.
Change-Id: Ib8cfb819083aca359e5b46b5757cb56cb0ea6533
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|
| 32d4f826 | 27-Apr-2016 |
danh-arm <dan.handley@arm.com> |
Merge pull request #597 from hzhuang1/emmc_v3.2
Emmc v3 |
| 08b375b0 | 21-Apr-2016 |
Haojian Zhuang <haojian.zhuang@linaro.org> |
Document: add MAX_IO_BLOCK_DEVICES platform macro
Add MAX_IO_BLOCK_DEVICES in porting guide. It's necessary to define
this macro to support io block device. With this macro, multiple
block devices c
Document: add MAX_IO_BLOCK_DEVICES platform macro
Add MAX_IO_BLOCK_DEVICES in porting guide. It's necessary to define
this macro to support io block device. With this macro, multiple
block devices could be opened at the same time. Each block device
stores its own state.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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|
| 3c2c72fa | 26-Apr-2016 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Doc: Fix the path to the xlat lib
The translation table library code has moved from lib/aarch64/ to
lib/xlat_tables/ since commit 3ca9928df but the Porting Guide still
points to the old location. Th
Doc: Fix the path to the xlat lib
The translation table library code has moved from lib/aarch64/ to
lib/xlat_tables/ since commit 3ca9928df but the Porting Guide still
points to the old location. This patch fixes this issue.
Change-Id: I983a9a100d70eacf6bac71725ffbb4bb5f3732b0
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|
| b96f77c6 | 15-Jun-2015 |
Michal Simek <michal.simek@xilinx.com> |
zynqmp: FSBL->ATF handover
Parse the parameter structure the FSBL populates, to populate the bl32
and bl33 image structures.
Cc: Sarat Chand Savitala <saratcha@xilinx.com>
Cc: petalinux-dev@xilinx.
zynqmp: FSBL->ATF handover
Parse the parameter structure the FSBL populates, to populate the bl32
and bl33 image structures.
Cc: Sarat Chand Savitala <saratcha@xilinx.com>
Cc: petalinux-dev@xilinx.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
[ SB
- pass pointers to structs instead of structs
- handle execution state parameter
- populate bl32 SPSR
- add documentation
- query bootmode and consider missing handoff parameters an error when
not in JTAG boot mode
]
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
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|
| 01555332 | 14-Apr-2016 |
Soren Brinkmann <soren.brinkmann@xilinx.com> |
zynqmp: Revise memory configuration options
Drop the current configuration options for selecting the location of
the ATF and TSP (ZYNQMP_ATF_LOCATION, ZYNQMP_TSP_RAM_LOCATION).
The new configuration
zynqmp: Revise memory configuration options
Drop the current configuration options for selecting the location of
the ATF and TSP (ZYNQMP_ATF_LOCATION, ZYNQMP_TSP_RAM_LOCATION).
The new configuration provides one default setup (ATF in OCM,
BL32 in DRAM). Additionally, the new configuration options
- ZYNQMP_ATF_MEM_BASE
- ZYNQMP_ATF_MEM_SIZE
- ZYNQMP_BL32_MEM_BASE
- ZYNQMP_BL32_MEM_SIZE
can be used to freely configure the memory locations used for ATF and
secure payload.
Also, allow setting the BL33 entry point via PRELOADED_BL33_BASE.
Cc: petalinux-dev@xilinx.com
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Alistair Francis <alistair.francis@xilinx.com>
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|
| 7607204c | 22-Apr-2016 |
danh-arm <dan.handley@arm.com> |
Merge pull request #601 from sandrine-bailleux-arm/sb/a57-errata-workarounds
Cortex-A57 errata workarounds |
| 86d8948c | 21-Apr-2016 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Doc: Add links to the A53/A57 Errata Notice documents
This patch adds links to the Cortex-A53 and Cortex-A57 MPCores
Software Developers Errata Notice documents in the ARM CPU Specific
Build Macros
Doc: Add links to the A53/A57 Errata Notice documents
This patch adds links to the Cortex-A53 and Cortex-A57 MPCores
Software Developers Errata Notice documents in the ARM CPU Specific
Build Macros document.
Change-Id: I0aa26d7f373026097ed012a02bc61ee2c5b9d6fc
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|
| adeecf92 | 21-Apr-2016 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Add support for Cortex-A57 erratum 833471 workaround
Change-Id: I86ac81ffd7cd094ce68c4cceb01c16563671a063 |
| 07288865 | 14-Apr-2016 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Add support for Cortex-A57 erratum 826977 workaround
Change-Id: Icaacd19c4cef9c10d02adcc2f84a4d7c97d4bcfa |
| 0b77197b | 14-Apr-2016 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Add support for Cortex-A57 erratum 829520 workaround
Change-Id: Ia2ce8aa752efb090cfc734c1895c8f2539e82439 |
| a8b1c769 | 14-Apr-2016 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Add support for Cortex-A57 erratum 828024 workaround
Change-Id: I632a8c5bb517ff89c69268e865be33101059be7d |
| 07e8942a | 21-Apr-2016 |
danh-arm <dan.handley@arm.com> |
Merge pull request #594 from jcastillo-arm/jc/user-guide
Update User Guide and move up to Linaro 16.02 |
| df22d602 | 14-Apr-2016 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Add support for Cortex-A57 erratum 826974 workaround
Change-Id: I45641551474f4c58c638aff8c42c0ab9a8ec78b4 |
| 9ff67fa6 | 26-Nov-2015 |
Gerald Lejeune <gerald.lejeune@st.com> |
Dump platform-defined regs in crash reporting
It is up to the platform to implement the new plat_crash_print_regs macro to
report all relevant platform registers helpful for troubleshooting.
plat_c
Dump platform-defined regs in crash reporting
It is up to the platform to implement the new plat_crash_print_regs macro to
report all relevant platform registers helpful for troubleshooting.
plat_crash_print_regs merges or calls previously defined plat_print_gic_regs
and plat_print_interconnect_regs macros for each existing platforms.
NOTE: THIS COMMIT REQUIRES ALL PLATFORMS THAT ENABLE THE `CRASH_REPORTING`
BUILD FLAG TO MIGRATE TO USE THE NEW `plat_crash_print_regs()` MACRO. BY
DEFAULT, `CRASH_REPORTING` IS ENABLED IN DEBUG BUILDS FOR ALL PLATFORMS.
Fixes: arm-software/tf-issues#373
Signed-off-by: Gerald Lejeune <gerald.lejeune@st.com>
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|
| ec0a975f | 17-Feb-2016 |
Juan Castillo <juan.castillo@arm.com> |
Update User Guide and move up to Linaro 16.02
This patch updates the TF User Guide, simplifying some of the steps
to build and run TF and trying to avoid duplicated information that
is already avail
Update User Guide and move up to Linaro 16.02
This patch updates the TF User Guide, simplifying some of the steps
to build and run TF and trying to avoid duplicated information that
is already available on the ARM Connected Community or the Linaro
website.
The recommended Linaro release is now 16.02.
Change-Id: I21db486d56a07bb10f5ee9a33014ccc59ca12986
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|
| 5d787dd9 | 08-Apr-2016 |
danh-arm <dan.handley@arm.com> |
Merge pull request #569 from Xilinx/zynqmp-v1
Support for Xilinx Zynq UltraScale+ MPSoC |
| c71a87a3 | 08-Apr-2016 |
danh-arm <dan.handley@arm.com> |
Merge pull request #587 from antonio-nino-diaz-arm/an/rename-bl33-base
Rename BL33_BASE and make it work with RESET_TO_BL31 |
| 68450a6d | 06-Apr-2016 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Rename BL33_BASE option to PRELOADED_BL33_BASE
To avoid confusion the build option BL33_BASE has been renamed to
PRELOADED_BL33_BASE, which is more descriptive of what it does and
doesn't get mistak
Rename BL33_BASE option to PRELOADED_BL33_BASE
To avoid confusion the build option BL33_BASE has been renamed to
PRELOADED_BL33_BASE, which is more descriptive of what it does and
doesn't get mistaken by similar names like BL32_BASE that work in a
completely different way.
NOTE: PLATFORMS USING BUILD OPTION `BL33_BASE` MUST CHANGE TO THE NEW
BUILD OPTION `PRELOADED_BL33_BASE`.
Change-Id: I658925ebe95406edf0325f15aa1752e1782aa45b
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|
| 7a0ae2f4 | 07-Apr-2016 |
danh-arm <dan.handley@arm.com> |
Merge pull request #584 from soby-mathew/sm/enable_scr_sif
Enable SCR_EL3.SIF bit |
| 91e8ae66 | 07-Apr-2016 |
danh-arm <dan.handley@arm.com> |
Merge pull request #578 from EvanLloyd/ejll/woa_make2
Make improvements for host environment portability |
| 5d29c760 | 07-Apr-2016 |
danh-arm <dan.handley@arm.com> |
Merge pull request #572 from jcastillo-arm/jc/tbb_nvcounter
TBB NVcounter support |