| e34606f2 | 24-Jun-2019 |
lauwal01 <lauren.wehrmeister@arm.com> |
Workaround for Neoverse N1 erratum 1130799
Neoverse N1 erratum 1130799 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the imp
Workaround for Neoverse N1 erratum 1130799
Neoverse N1 erratum 1130799 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR2_EL1 system register.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: I252bc45f9733443ba0503fefe62f50fdea61da6d
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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| a601afe1 | 24-Jun-2019 |
lauwal01 <lauren.wehrmeister@arm.com> |
Workaround for Neoverse N1 erratum 1073348
Neoverse N1 erratum 1073348 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the imp
Workaround for Neoverse N1 erratum 1073348
Neoverse N1 erratum 1073348 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR_EL1 system register, which disables static prediction.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: I674126c0af6e068eecb379a190bcf7c75dcbca8e
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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| 0d220b35 | 01-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "banned_api_list" into integration
* changes:
Fix the License header template in imx_aipstz.c
docs: Add the list of banned/use with caution APIs |
| 140c8311 | 20-Jun-2019 |
Soby Mathew <soby.mathew@arm.com> |
docs: Add the list of banned/use with caution APIs
Credit to sam.ellis@arm.com for the input to create the list.
Change-Id: Id70a8eddc5f2490811bebb278482c61950f10cce
Signed-off-by: Soby Mathew <sob
docs: Add the list of banned/use with caution APIs
Credit to sam.ellis@arm.com for the input to create the list.
Change-Id: Id70a8eddc5f2490811bebb278482c61950f10cce
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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| 1b779c8c | 25-Jun-2019 |
John Tsichritzis <john.tsichritzis@arm.com> |
Merge "doc: Fix typo in file interrupt-framework-design.rst" into integration |
| 2645fceb | 24-Jun-2019 |
John Tsichritzis <john.tsichritzis@arm.com> |
Fix links in documentation
Change-Id: Ifef4d634b4a34d23f42f61df5e326a1cc05d3844
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> |
| 36a5acfd | 22-Jun-2019 |
Peng Donglin <dolinux.peng@gmail.com> |
doc: Fix typo in file interrupt-framework-design.rst
Signed-off-by: Peng Donglin <dolinux.peng@gmail.com>
Change-Id: I459e7d056735222f6f34e275dbdaf9a389d193fc |
| f56734fe | 20-Jun-2019 |
John Tsichritzis <john.tsichritzis@arm.com> |
Merge "doc: Isolate security-related build options" into integration |
| 196fa6c8 | 20-May-2019 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: update doc for U-Boot compilation
U-Boot should be compiled with stm32mp15_trusted_defconfig which is
supported since tag v2019.07-rc1 with commit [1].
The creation of the U-Boot binary w
stm32mp1: update doc for U-Boot compilation
U-Boot should be compiled with stm32mp15_trusted_defconfig which is
supported since tag v2019.07-rc1 with commit [1].
The creation of the U-Boot binary with stm32 header is done at U-Boot
compilation step, it is no more required to call the extra command.
[1] https://git.denx.de/?p=u-boot.git;a=commit;h=015289580f81
Change-Id: Ia875c22184785fc2e02ad07993a649069cd5ce34
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 2e302371 | 05-Jun-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
doc: Isolate security-related build options
Reference security specific build options from the user guide.
Change-Id: I0e1efbf47d914cf3c473104175c702ff1a80eb67
Signed-off-by: Ambroise Vincent <ambr
doc: Isolate security-related build options
Reference security specific build options from the user guide.
Change-Id: I0e1efbf47d914cf3c473104175c702ff1a80eb67
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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|
| 4143ed8f | 11-Jun-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "Update maintainers list" into integration |
| 156dfbce | 10-Jun-2019 |
John Tsichritzis <john.tsichritzis@arm.com> |
Update maintainers list
Also sort alphabetically the links at the bottom, a couple of them were
not sorted.
Change-Id: I49a1dbe9e56a36c5fdbace8e4c8b9a5270bc2984
Signed-off-by: John Tsichritzis <joh
Update maintainers list
Also sort alphabetically the links at the bottom, a couple of them were
not sorted.
Change-Id: I49a1dbe9e56a36c5fdbace8e4c8b9a5270bc2984
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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|
| dc593ddc | 10-Jun-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "doc: Document E and W build options" into integration |
| 5f5d0763 | 20-May-2019 |
Andre Przywara <andre.przywara@arm.com> |
Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703
Neoverse N1 erratum 1315703 is a Cat A (rare) erratum [1], present in
older revisions of the Neoverse N1 processor core.
The workaro
Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703
Neoverse N1 erratum 1315703 is a Cat A (rare) erratum [1], present in
older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined CPUACTLR2_EL1
system register, which will disable the load-bypass-store feature.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdocpjdoc-466751330-1032/index.html
Change-Id: I5c708dbe0efa4daa0bcb6bd9622c5efe19c03af9
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| 08455b97 | 06-Jun-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
doc: Document E and W build options
Change-Id: I0d9dbef7041fcf950bcafcdbbc17c72b4dea9e40
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> |
| 49d969bb | 03-Jun-2019 |
John Tsichritzis <john.tsichritzis@arm.com> |
Merge "doc: Enable automatic labels for page titles" into integration |
| d2944096 | 03-Jun-2019 |
John Tsichritzis <john.tsichritzis@arm.com> |
Add information about the mailing list in the docs
Change-Id: I41ce5323c33a81db13c5cc40de1ac4e221a10cd8
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> |
| 008c843c | 31-May-2019 |
John Tsichritzis <john.tsichritzis@arm.com> |
Removing IRC related info from the documentation
Change-Id: I5cf8c70a304bf5869cbeb12fa8d39171cff48ebd
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> |
| c4e4df35 | 17-May-2019 |
Paul Beesley <paul.beesley@arm.com> |
doc: Enable automatic labels for page titles
Automatic labelling of document titles is a prerequisite for
converting the format of cross-document links. Sphinx will
generate (via the enabled extensi
doc: Enable automatic labels for page titles
Automatic labelling of document titles is a prerequisite for
converting the format of cross-document links. Sphinx will
generate (via the enabled extension) a hidden link target for
each document title and this can be referred to later, from
another page, to link to the target.
The plugin options being used require Sphinx >= 2.0.0 so a
requirements.txt file has been added. This file is used with
the pip package manager for Python so that the correct
dependencies are installed.
Change-Id: Ic2049db5804aa4a6447608ba4299de958ce0a87d
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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| f6ad51c8 | 28-May-2019 |
John Tsichritzis <john.tsichritzis@arm.com> |
Further fixes to documentation links
Change-Id: Ib021c721652d96f6c06ea18741f19a72bba1d00f
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> |
| 84167417 | 29-May-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge "Cortex-A55: workarounds for errata 1221012" into integration |
| 9af07df0 | 28-May-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Cortex-A55: workarounds for errata 1221012
The workaround is added to the Cortex-A55 cpu specific file. The
workaround is disabled by default and have to be explicitly enabled by
the platform integr
Cortex-A55: workarounds for errata 1221012
The workaround is added to the Cortex-A55 cpu specific file. The
workaround is disabled by default and have to be explicitly enabled by
the platform integrator.
Change-Id: I3e6fd10df6444122a8ee7d08058946ff1cc912f8
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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| 566d15e8 | 28-May-2019 |
John Tsichritzis <john.tsichritzis@arm.com> |
Fix documentation links
Change-Id: Ic09e74f22b43fba51ee17cd02b5e1dc5d8e0bb63
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> |
| 508a48bb | 24-May-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge "Add support for Branch Target Identification" into integration |
| 9fc59639 | 24-May-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Add support for Branch Target Identification
This patch adds the functionality needed for platforms to provide
Branch Target Identification (BTI) extension, introduced to AArch64
in Armv8.5-A by add
Add support for Branch Target Identification
This patch adds the functionality needed for platforms to provide
Branch Target Identification (BTI) extension, introduced to AArch64
in Armv8.5-A by adding BTI instruction used to mark valid targets
for indirect branches. The patch sets new GP bit [50] to the stage 1
Translation Table Block and Page entries to denote guarded EL3 code
pages which will cause processor to trap instructions in protected
pages trying to perform an indirect branch to any instruction other
than BTI.
BTI feature is selected by BRANCH_PROTECTION option which supersedes
the previous ENABLE_PAUTH used for Armv8.3-A Pointer Authentication
and is disabled by default. Enabling BTI requires compiler support
and was tested with GCC versions 9.0.0, 9.0.1 and 10.0.0.
The assembly macros and helpers are modified to accommodate the BTI
instruction.
This is an experimental feature.
Note. The previous ENABLE_PAUTH build option to enable PAuth in EL3
is now made as an internal flag and BRANCH_PROTECTION flag should be
used instead to enable Pointer Authentication.
Note. USE_LIBROM=1 option is currently not supported.
Change-Id: Ifaf4438609b16647dc79468b70cd1f47a623362e
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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