| 21c4f56f | 11-Feb-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "lm/fconf" into integration
* changes:
arm-io: Panic in case of io setup failure
MISRA fix: Use boolean essential type
fconf: Add documentation
fconf: Move platform
Merge changes from topic "lm/fconf" into integration
* changes:
arm-io: Panic in case of io setup failure
MISRA fix: Use boolean essential type
fconf: Add documentation
fconf: Move platform io policies into fconf
fconf: Add mbedtls shared heap as property
fconf: Add TBBR disable_authentication property
fconf: Add dynamic config DTBs info as property
fconf: Populate properties from dtb during bl2 setup
fconf: Load config dtb from bl1
fconf: initial commit
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|
| c8e0f950 | 10-Feb-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "Make PAC demangling more generic" into integration |
| 65f6c3e9 | 10-Feb-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "amlogic/axg" into integration
* changes:
amlogic: axg: Add a build flag when using ATOS as BL32
amlogic: axg: Add support for the A113D (AXG) platform |
| 68c76088 | 06-Feb-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Make PAC demangling more generic
At the moment, address demangling is only used by the backtrace
functionality. However, at some point, other parts of the TF-A
codebase may want to use it.
The 'dema
Make PAC demangling more generic
At the moment, address demangling is only used by the backtrace
functionality. However, at some point, other parts of the TF-A
codebase may want to use it.
The 'demangle_address' function is replaced with a single XPACI
instruction which is also added in 'do_crash_reporting()'.
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Change-Id: I4424dcd54d5bf0a5f9b2a0a84c4e565eec7329ec
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|
| 4d37aa76 | 26-Dec-2019 |
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> |
plat/arm/sgi: introduce number of chips macro
Introduce macro 'CSS_SGI_CHIP_COUNT' to allow Arm CSS platforms with
multi-chip support to define number of chiplets on the platform. By
default, this f
plat/arm/sgi: introduce number of chips macro
Introduce macro 'CSS_SGI_CHIP_COUNT' to allow Arm CSS platforms with
multi-chip support to define number of chiplets on the platform. By
default, this flag is set to 1 and does not affect the existing single
chip platforms.
For multi-chip platforms, override the default value of
CSS_SGI_CHIP_COUNT with the number of chiplets supported on the
platform. As an example, the command below sets the number of chiplets
to two on the RD-N1-Edge multi-chip platform:
export CROSS_COMPILE=<path-to-cross-compiler>
make PLAT=rdn1edge CSS_SGI_CHIP_COUNT=2 ARCH=aarch64 all
Change-Id: If364dc36bd34b30cc356f74b3e97633933e6c8ee
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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| 326150b9 | 08-Nov-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
fconf: Add documentation
Change-Id: I606f9491fb6deebc6845c5b9d7db88fc5c895bd9
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> |
| 0a6e7e3b | 24-Oct-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
fconf: Move platform io policies into fconf
Use the firmware configuration framework to store the io_policies
information inside the configuration device tree instead of the static
structure in the
fconf: Move platform io policies into fconf
Use the firmware configuration framework to store the io_policies
information inside the configuration device tree instead of the static
structure in the code base.
The io_policies required by BL1 can't be inside the dtb, as this one is
loaded by BL1, and only available at BL2.
This change currently only applies to FVP platform.
Change-Id: Ic9c1ac3931a4a136aa36f7f58f66d3764c1bfca1
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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|
| 350aed43 | 07-Feb-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "Adds option to read ROTPK from registers for FVP" into integration |
| a6ffddec | 06-Dec-2019 |
Max Shvetsov <maksims.svecovs@arm.com> |
Adds option to read ROTPK from registers for FVP
Enables usage of ARM_ROTPK_LOCATION=regs for FVP board.
Removes hard-coded developer keys. Instead, setting
ARM_ROTPK_LOCATION=devel_* takes keys fro
Adds option to read ROTPK from registers for FVP
Enables usage of ARM_ROTPK_LOCATION=regs for FVP board.
Removes hard-coded developer keys. Instead, setting
ARM_ROTPK_LOCATION=devel_* takes keys from default directory.
In case of ROT_KEY specified - generates a new hash and replaces the
original.
Note: Juno board was tested by original feature author and was not tested
for this patch since we don't have access to the private key. Juno
implementation was moved to board-specific file without changing
functionality. It is not known whether byte-swapping is still needed
for this platform.
Change-Id: I0fdbaca0415cdcd78f3a388551c2e478c01ed986
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
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|
| e63f5d12 | 16-May-2019 |
Paul Beesley <paul.beesley@arm.com> |
doc: Split and expand coding style documentation
This patch expands the coding style documentation, splitting it
into two documents: the core style rules and extended guidelines.
Note that it does n
doc: Split and expand coding style documentation
This patch expands the coding style documentation, splitting it
into two documents: the core style rules and extended guidelines.
Note that it does not redefine or change the coding style (aside
from section 4.6.2) - generally, it is only documenting the
existing style in more detail.
The aim is for the coding style to be more readable and, in turn,
for it to be followed by more people. We can use this as a more
concrete reference when discussing the accepted style with external
contributors.
Change-Id: I87405ace9a879d7f81e6b0b91b93ca69535e50ff
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com>
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|
| 3a415eb9 | 06-Feb-2020 |
György Szing <gyorgy.szing@arm.com> |
Merge "doc: Remove backquotes from external hyperlinks" into integration |
| 72d2535a | 27-Jan-2020 |
Carlo Caione <ccaione@baylibre.com> |
amlogic: axg: Add a build flag when using ATOS as BL32
BL2 is unconditionally setting 0 (OPTEE_AARCH64) in arg0 even when the
BL32 image is 32bit (OPTEE_AARCH32). This is causing the boot to hang
wh
amlogic: axg: Add a build flag when using ATOS as BL32
BL2 is unconditionally setting 0 (OPTEE_AARCH64) in arg0 even when the
BL32 image is 32bit (OPTEE_AARCH32). This is causing the boot to hang
when ATOS (32bit Amlogic BL32 binary-only TEE OS) is used.
Since we are not aware of any Amlogic platform shipping a 64bit version
of ATOS we can hardcode OPTEE_AARCH32 / MODE_RW_32 when using ATOS.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Iaea47cf6dc48bf8a646056761f02fb81b41c78a3
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|
| afd241e7 | 24-Jan-2020 |
Carlo Caione <ccaione@baylibre.com> |
amlogic: axg: Add support for the A113D (AXG) platform
Introduce the preliminary support for the Amlogic A113D (AXG) SoC.
This port is a minimal implementation of BL31 capable of booting
mainline U
amlogic: axg: Add support for the A113D (AXG) platform
Introduce the preliminary support for the Amlogic A113D (AXG) SoC.
This port is a minimal implementation of BL31 capable of booting
mainline U-Boot, Linux and chainloading BL32 (ATOS).
Tested on a A113D board.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ic4548fa2f7c48d61b485b2a6517ec36c53c20809
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|
| 8d52e16b | 03-Feb-2020 |
Imre Kis <imre.kis@arm.com> |
doc: Remove backquotes from external hyperlinks
Since Sphinx 2.3.0 backquotes are replaced to \textasciigrave{} during
building latexpdf. Using this element in a \sphinxhref{} breaks the
build. In o
doc: Remove backquotes from external hyperlinks
Since Sphinx 2.3.0 backquotes are replaced to \textasciigrave{} during
building latexpdf. Using this element in a \sphinxhref{} breaks the
build. In order to avoid this error backquotes must not be used in
external hyperlinks.
Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: Ie3cf454427e3d5a7b7f9829b42be45aebda7f0dd
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|
| 62038be7 | 26-Dec-2019 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
doc: qemu: fix and update documentation
The current URL for QEMU_EFI.fd is not found. Update the link to
point to the new one.
If you run the shell command as instructed, you will see this error:
doc: qemu: fix and update documentation
The current URL for QEMU_EFI.fd is not found. Update the link to
point to the new one.
If you run the shell command as instructed, you will see this error:
qemu-system-aarch64: keep_bootcon: Could not open 'keep_bootcon': No such file or directory
The part "console=ttyAMA0,38400 keep_bootcon root=/dev/vda2" is the
kernel parameter, so it must be quoted.
As of writing, QEMU v4.2.0 is the latest, but it does not work for
TF-A (It has been fixed in the mainline.) QEMU v4.1.0 works fine.
With those issues addressed, I succeeded in booting the latest kernel.
Tested with QEMU v4.1.0 and Linux 5.5 (defconfig with no modification).
Update the tested versions.
Change-Id: Ic85db0e688d67b1803ff890047d37de3f3db2daa
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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|
| 989429e8 | 31-Jan-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "Add support for documentation build as a target in Makefile" into integration |
| dcd03ce7 | 30-Jan-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "sb/select-cot" into integration
* changes:
Introduce COT build option
cert_create: Remove references to TBBR in common code
cert_create: Introduce COT build option
Merge changes from topic "sb/select-cot" into integration
* changes:
Introduce COT build option
cert_create: Remove references to TBBR in common code
cert_create: Introduce COT build option
cert_create: Introduce TBBR CoT makefile
show more ...
|
| 3bff910d | 15-Jan-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Introduce COT build option
Allows to select the chain of trust to use when the Trusted Boot feature
is enabled. This affects both the cert_create tool and the firmware
itself.
Right now, the only a
Introduce COT build option
Allows to select the chain of trust to use when the Trusted Boot feature
is enabled. This affects both the cert_create tool and the firmware
itself.
Right now, the only available CoT is TBBR.
Change-Id: I7ab54e66508a1416cb3fcd3dfb0f055696763b3d
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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|
| 6de32378 | 28-Jan-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Add support for documentation build as a target in Makefile
Command to build HTML-formatted pages from docs:
make doc
Change-Id: I4103c804b3564fe67d8fc5a3373679daabf3f2e9
Signed-off-by: Madhukar Pa
Add support for documentation build as a target in Makefile
Command to build HTML-formatted pages from docs:
make doc
Change-Id: I4103c804b3564fe67d8fc5a3373679daabf3f2e9
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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|
| 8efec9e0 | 29-Jan-2020 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes I0fb7cf79,Ia8eb4710 into integration
* changes:
qemu: Implement qemu_system_off via semihosting.
qemu: Support ARM_LINUX_KERNEL_AS_BL33 to pass FDT address. |
| 8c105290 | 23-Jan-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Measured Boot: add function for hash calculation
This patch adds 'calc_hash' function using Mbed TLS library
required for Measured Boot support.
Change-Id: Ifc5aee0162d04db58ec6391e0726a526f29a52bb
Measured Boot: add function for hash calculation
This patch adds 'calc_hash' function using Mbed TLS library
required for Measured Boot support.
Change-Id: Ifc5aee0162d04db58ec6391e0726a526f29a52bb
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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|
| 91ff490d | 28-Jan-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "Neovers N1: added support to update presence of External LLC" into integration |
| f2d6b4ee | 24-Jan-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Neovers N1: added support to update presence of External LLC
CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external
last level cache(LLC) in the system, the reset value is internal L
Neovers N1: added support to update presence of External LLC
CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external
last level cache(LLC) in the system, the reset value is internal LLC.
To cater for the platforms(like N1SDP) which has external LLC present
introduce a new build option 'NEOVERSE_N1_EXTERNAL_LLC' which can be
enabled by platform port.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ibf475fcd6fd44401897a71600f4eafe989921363
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|
| d974301d | 17-Jan-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
TSP: add PIE support
This implementation simply mimics that of BL31.
Change-Id: Ibbaa4ca012d38ac211c52b0b3e97449947160e07
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
| 69af7fcf | 17-Jan-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
BL2_AT_EL3: add PIE support
This implementation simply mimics that of BL31.
I did not implement the ENABLE_PIE support for BL2_IN_XIP_MEM=1 case.
It would make the linker script a bit uglier.
Chan
BL2_AT_EL3: add PIE support
This implementation simply mimics that of BL31.
I did not implement the ENABLE_PIE support for BL2_IN_XIP_MEM=1 case.
It would make the linker script a bit uglier.
Change-Id: If3215abd99f2758dfb232e44b50320d04eba808b
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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|