| d1c54e5b | 24-Jun-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
doc: Update arg usage for BL2 and BL31 setup functions
Updated the porting guide for the usage of received arguments
in BL2 and BL32 setup functions in case of Arm platform.
Signed-off-by: Manish V
doc: Update arg usage for BL2 and BL31 setup functions
Updated the porting guide for the usage of received arguments
in BL2 and BL32 setup functions in case of Arm platform.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ia83a5607fed999819d25e49322b3bfb5db9425c0
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|
| e555787b | 21-Jun-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
doc: Update BL1 and BL2 boot flow
Updated the document for BL1 and BL2 boot flow to capture
below changes made in FCONF
1. Loading of fw_config and tb_fw_config images by BL1.
2. Population of fw_c
doc: Update BL1 and BL2 boot flow
Updated the document for BL1 and BL2 boot flow to capture
below changes made in FCONF
1. Loading of fw_config and tb_fw_config images by BL1.
2. Population of fw_config and tb_fw_config by BL2.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ifea5c61d520ff1de834c279ce1759b53448303ba
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|
| 99bcae5e | 26-Jun-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "fw_config_handoff" into integration
* changes:
doc: Update memory layout for firmware configuration area
plat/arm: Increase size of firmware configuration area
plat/a
Merge changes from topic "fw_config_handoff" into integration
* changes:
doc: Update memory layout for firmware configuration area
plat/arm: Increase size of firmware configuration area
plat/arm: Load and populate fw_config and tb_fw_config
fconf: Handle error from fconf_load_config
plat/arm: Update the fw_config load call and populate it's information
fconf: Allow fconf to load additional firmware configuration
fconf: Clean confused naming between TB_FW and FW_CONFIG
tbbr/dualroot: Add fw_config image in chain of trust
cert_tool: Update cert_tool for fw_config image support
fiptool: Add fw_config in FIP
plat/arm: Rentroduce tb_fw_config device tree
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|
| 0e0521bd | 02-Jun-2020 |
johpow01 <john.powell@arm.com> |
Workaround for Neoverse N1 erratum 1800710
Neoverse N1 erratum 1800710 is a Cat B erratum, present in older
revisions of the Neoverse N1 processor core. The workaround is to
set a bit in the ECTLR_
Workaround for Neoverse N1 erratum 1800710
Neoverse N1 erratum 1800710 is a Cat B erratum, present in older
revisions of the Neoverse N1 processor core. The workaround is to
set a bit in the ECTLR_EL1 system register, which disables allocation
of splintered pages in the L2 TLB.
This errata is explained in this SDEN:
https://static.docs.arm.com/sden885747/f/Arm_Neoverse_N1_MP050_Software_Developer_Errata_Notice_v21.pdf
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ie5b15c8bc3235e474a06a57c3ec70684361857a6
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|
| 33fe493a | 25-Jun-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "Redirect security incident report to TrustedFirmware.org" into integration |
| f112d3ef | 25-Jun-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "doc: Add a binding document for COT descriptors" into integration |
| 62bbfe82 | 03-Jun-2020 |
johpow01 <john.powell@arm.com> |
Workaround for Cortex A77 erratum 1800714
Cortex A77 erratum 1800714 is a Cat B erratum, present in older
revisions of the Cortex A77 processor core. The workaround is to
set a bit in the ECTLR_EL1
Workaround for Cortex A77 erratum 1800714
Cortex A77 erratum 1800714 is a Cat B erratum, present in older
revisions of the Cortex A77 processor core. The workaround is to
set a bit in the ECTLR_EL1 system register, which disables allocation
of splintered pages in the L2 TLB.
Since this is the first errata workaround implemented for Cortex A77,
this patch also adds the required cortex_a77_reset_func in the file
lib/cpus/aarch64/cortex_a77.S.
This errata is explained in this SDEN:
https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I844de34ee1bd0268f80794e2d9542de2f30fd3ad
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|
| 089fc624 | 13-Jun-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
doc: Update memory layout for firmware configuration area
Captured the increase in firmware configuration area from
4KB to 8kB in memory layout document. Updated the documentation
to provide details
doc: Update memory layout for firmware configuration area
Captured the increase in firmware configuration area from
4KB to 8kB in memory layout document. Updated the documentation
to provide details about fw_config separately.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ifbec443ced479301be65827b49ff4fe447e9109f
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|
| 1367cc19 | 22-Jun-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Redirect security incident report to TrustedFirmware.org
All projects under the TrustedFirmware.org project now use the same
security incident process, therefore update the disclosure/vulnerability
Redirect security incident report to TrustedFirmware.org
All projects under the TrustedFirmware.org project now use the same
security incident process, therefore update the disclosure/vulnerability
reporting information in the TF-A documentation.
------------------------------------------------------------------------
/!\ IMPORTANT /!\
Please note that the email address to send these reports to has changed.
Please do *not* use trusted-firmware-security@arm.com anymore.
Similarly, the PGP key provided to encrypt emails to the security email
alias has changed as well. Please do *not* use the former one provided
in the TF-A source tree. It is recommended to remove it from your
keyring to avoid any mistake. Please use the new key provided on
TrustedFirmware.org from now on.
------------------------------------------------------------------------
Change-Id: I14eb61017ab99182f1c45d1e156b96d5764934c1
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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|
| ccf58632 | 23-Jun-2020 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes Ifc34f2e9,Iefd58159 into integration
* changes:
Workaround for Cortex A76 erratum 1800710
Workaround for Cortex A76 erratum 1791580 |
| ebd34bea | 23-Jun-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
doc: Add a binding document for COT descriptors
Added a binding document for COT descriptors which is going
to be used in order to create COT desciptors at run-time.
Signed-off-by: Manish V Badarkh
doc: Add a binding document for COT descriptors
Added a binding document for COT descriptors which is going
to be used in order to create COT desciptors at run-time.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ic54519b0e16d145cd1609274a00b137a9194e8dd
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|
| dcbfbcb5 | 02-Jun-2020 |
johpow01 <john.powell@arm.com> |
Workaround for Cortex A76 erratum 1800710
Cortex A76 erratum 1800710 is a Cat B erratum, present in older
revisions of the Cortex A76 processor core. The workaround is to
set a bit in the ECTLR_EL1
Workaround for Cortex A76 erratum 1800710
Cortex A76 erratum 1800710 is a Cat B erratum, present in older
revisions of the Cortex A76 processor core. The workaround is to
set a bit in the ECTLR_EL1 system register, which disables allocation
of splintered pages in the L2 TLB.
This errata is explained in this SDEN:
https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ifc34f2e9e053dcee6a108cfb7df7ff7f497c9493
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|
| d7b08e69 | 29-May-2020 |
johpow01 <john.powell@arm.com> |
Workaround for Cortex A76 erratum 1791580
Cortex A76 erratum 1791580 is a Cat B erratum present in earlier
revisions of the Cortex A76. The workaround is to set a bit in the
implementation defined C
Workaround for Cortex A76 erratum 1791580
Cortex A76 erratum 1791580 is a Cat B erratum present in earlier
revisions of the Cortex A76. The workaround is to set a bit in the
implementation defined CPUACTLR2 register, which forces atomic store
operations to write-back memory to be performed in the L1 data cache.
This errata is explained in this SDEN:
https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Iefd58159b3f2e2286138993317b98e57dc361925
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|
| 5a40d70f | 31-Mar-2019 |
Konstantin Porotchkin <kostap@marvell.com> |
drivers: marvell: add support for mapping the entire LLC to SRAM
Add llc_sram_enable() and llc_sram_disable() APIs to Marvell
cache_lls driver.
Add LLC_SRAM definition to Marvell common makefile - d
drivers: marvell: add support for mapping the entire LLC to SRAM
Add llc_sram_enable() and llc_sram_disable() APIs to Marvell
cache_lls driver.
Add LLC_SRAM definition to Marvell common makefile - disabled
by the default.
Add description of LLC_SRAM flag to the build documentation.
Change-Id: Ib348e09752ce1206d29268ef96c9018b781db182
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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|
| 3768fecf | 19-Jun-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
TF-A: Add ARMv8.5 'bti' build option
This patch adds BRANCH_PROTECTION = 4 'bti' build option
which turns on branch target identification mechanism.
Change-Id: I32464a6b51726a100519f449a95aea5331f0
TF-A: Add ARMv8.5 'bti' build option
This patch adds BRANCH_PROTECTION = 4 'bti' build option
which turns on branch target identification mechanism.
Change-Id: I32464a6b51726a100519f449a95aea5331f0e82d
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
show more ...
|
| 9935047b | 17-Jun-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I80316689,I23cac4fb,If911e7de,I169ff358,I4e040cd5, ... into integration
* changes:
ddr: a80x0: add DDR 32-bit ECC mode support
ble: ap807: improve PLL configuration sequence
ble:
Merge changes I80316689,I23cac4fb,If911e7de,I169ff358,I4e040cd5, ... into integration
* changes:
ddr: a80x0: add DDR 32-bit ECC mode support
ble: ap807: improve PLL configuration sequence
ble: ap807: clean-up PLL configuration sequence
ddr: a80x0: add DDR 32-bit mode support
plat: marvell: mci: perform mci link tuning for all mci interfaces
plat: marvell: mci: use more meaningful name for mci link tuning
plat: marvell: a8k: remove wrong or unnecessary comments
plat: marvell: ap807: enable snoop filter for ap807
plat: marvell: ap807: update configuration space of each CP
plat: marvell: ap807: use correct address for MCIx4 register
plat: marvell: add support for PLL 2.2GHz mode
plat: marvell: armada: make a8k_common.mk and mss_common.mk more generic
marvell: armada: add extra level in marvell platform hierarchy
show more ...
|
| 5eeb091a | 16-Jun-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "tegra194-ras-handling" into integration
* changes:
Tegra194: ras: verbose prints for SErrors
Prevent RAS register access from lower ELs
Tegra194: SiP: clear RAS corre
Merge changes from topic "tegra194-ras-handling" into integration
* changes:
Tegra194: ras: verbose prints for SErrors
Prevent RAS register access from lower ELs
Tegra194: SiP: clear RAS corrected error records
Tegra194: add RAS exception handling
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|
| 4f4fc188 | 15-Jun-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Add Raghu Krishnamurthy as a TF-A maintainer
Change-Id: I3726f42f8f3de0cd88bd77a0f9d92a710649d18c
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> |
| fbc44bd1 | 12-Jun-2020 |
Varun Wadekar <vwadekar@nvidia.com> |
Prevent RAS register access from lower ELs
This patch adds a build config 'RAS_TRAP_LOWER_EL_ERR_ACCESS' to set
SCR_EL3.TERR during CPU boot. This bit enables trapping RAS register
accesses from EL1
Prevent RAS register access from lower ELs
This patch adds a build config 'RAS_TRAP_LOWER_EL_ERR_ACCESS' to set
SCR_EL3.TERR during CPU boot. This bit enables trapping RAS register
accesses from EL1 or EL2 to EL3.
RAS_TRAP_LOWER_EL_ERR_ACCESS is disabled by default.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ifb0fb0afedea7dd2a29a0b0491a1161ecd241438
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|
| 10640d24 | 09-Jun-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "GICv3: GIC-600: Detect GIC-600 at runtime" into integration |
| 452d5e5e | 02-Jun-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
plat/fvp: Add support for dynamic description of secure interrupts
Using the fconf framework, the Group 0 and Group 1 secure interrupt
descriptors are moved to device tree and retrieved in runtime.
plat/fvp: Add support for dynamic description of secure interrupts
Using the fconf framework, the Group 0 and Group 1 secure interrupt
descriptors are moved to device tree and retrieved in runtime. This
feature is enabled by the build flag SEC_INT_DESC_IN_FCONF.
Change-Id: I360c63a83286c7ecc2426cd1ff1b4746d61e633c
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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|
| b4ad365a | 25-Mar-2020 |
Andre Przywara <andre.przywara@arm.com> |
GICv3: GIC-600: Detect GIC-600 at runtime
The only difference between GIC-500 and GIC-600 relevant to TF-A is the
differing power management sequence.
A certain GIC implementation is detectable at r
GICv3: GIC-600: Detect GIC-600 at runtime
The only difference between GIC-500 and GIC-600 relevant to TF-A is the
differing power management sequence.
A certain GIC implementation is detectable at runtime, for instance by
checking the IIDR register. Let's add that test before initiating the
GIC-600 specific sequence, so the code can be used on both GIC-600 and
GIC-500 chips alike, without deciding on a GIC chip at compile time.
This means that the GIC-500 "driver" is now redundant. To allow minimal
platform support, add a switch to disable GIC-600 support.
Change-Id: I17ea97d9fb05874772ebaa13e6678b4ba3415557
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
show more ...
|
| 57adbf37 | 25-Feb-2019 |
Alex Leibovich <alexl@marvell.com> |
ddr: a80x0: add DDR 32-bit mode support
This commit introduces 32-bit DDR topology map initialization.
For that purpose a new DDR32 build flag is added, with
according documentation update.
Change-
ddr: a80x0: add DDR 32-bit mode support
This commit introduces 32-bit DDR topology map initialization.
For that purpose a new DDR32 build flag is added, with
according documentation update.
Change-Id: I169ff358c2923afd984e27bc126dc551dcaefc01
Signed-off-by: Alex Leibovich <alexl@marvell.com>
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|
| a2847172 | 05-Nov-2019 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
marvell: armada: add extra level in marvell platform hierarchy
This commit is a preparation for upcoming support for OcteonTX and
OcteonTX2 product families. Armada platform related files (docs,
pla
marvell: armada: add extra level in marvell platform hierarchy
This commit is a preparation for upcoming support for OcteonTX and
OcteonTX2 product families. Armada platform related files (docs,
plat, include/plat) are moved to the new "armada" sub-folder.
Change-Id: Icf03356187078ad6a2e56c9870992be3ca4c9655
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
show more ...
|
| 3f35709c | 01-Jun-2020 |
Jimmy Brisson <jimmy.brisson@arm.com> |
Rename Cortex-Hercules to Cortex-A78
Change-Id: I89b90cbdfc8f2aa898b4f3676a4764f060f8e138
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com> |