fix(optee): address late comments and fix bad rc

There were some late comments to the prior change (18635) which are
address in this commit. There was also an invalid return value check
which was ch

fix(optee): address late comments and fix bad rc

There were some late comments to the prior change (18635) which are
address in this commit. There was also an invalid return value check
which was changed and the wrong result was being returned via the SMC
call for loading OP-TEE which is now fixed.

Signed-off-by: Jeffrey Kardatzke <jkardatzke@google.com>
Change-Id: I883ddf966662549a3ef9c801a2d4f47709422332

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feat(fconf): rename 'ns-load-address' to 'secondary-load-address'

The 'ns-load-address' property has been renamed to 'secondary-load-
address' in order to make it more generic. It can be used to cop

feat(fconf): rename 'ns-load-address' to 'secondary-load-address'

The 'ns-load-address' property has been renamed to 'secondary-load-
address' in order to make it more generic. It can be used to copy
the configuration to any location, be it root, secure, or non-secure.

Change-Id: I122508e155ccd99082296be3f6b8db2f908be221
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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docs(qemu): delineate flash based boot method

Make the language around the explanation for booting via secure flash
clearer. Provide details into the intent of the options given to QEMU.

Change-Id:

docs(qemu): delineate flash based boot method

Make the language around the explanation for booting via secure flash
clearer. Provide details into the intent of the options given to QEMU.

Change-Id: Ia573b900aaa2346cad4f82191110b978f9bd5481
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(gicv3): enlarge the range for intr_num of structure interrupt_prop_t

As the max ESPI can be 5119, so enlarge the intr_num range of
structure interrupt_prop_t. After the patch the ESPI can be ad

feat(gicv3): enlarge the range for intr_num of structure interrupt_prop_t

As the max ESPI can be 5119, so enlarge the intr_num range of
structure interrupt_prop_t. After the patch the ESPI can be add to
this macro:
define PLATFORM_G1S_PROPS(grp) \
INTR_PROP_DESC(197 - 32 + 4576, GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(199 - 32 + 4576, GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE)

The firmware-design.rst will be updated accordingly.

Signed-off-by: Ming Huang <huangming@linux.alibaba.com>
Change-Id: Ic923868bb1b00c017410dc2aeabfda58ee54782f

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docs: add interrupts-target field to sp manifest

In order to support the ability to target a SPI interrupt to a
particular core, an impdef field "interrupts-target" has been added to
associate and i

docs: add interrupts-target field to sp manifest

In order to support the ability to target a SPI interrupt to a
particular core, an impdef field "interrupts-target" has been added to
associate and interrupt id with an mpidr. The field is optional and if
not provided, existing SPMC behavior of routing to boot strap core is
maintained.

Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
Change-Id: I78ccfb45cd9b411cca4b36ff940064fc9dcd1622

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Merge "feat(optee): add loading OP-TEE image via an SMC" into integration

Merge changes from topic "xlnx_feat_chores" into integration

* changes:
chore(xilinx): update print information
feat(versal-net): add jtag dcc support

Merge changes I1b092bc1,Ifc2461b4,I5176caa5 into integration

* changes:
docs(rme): update RMM-EL3 Boot Manifest structure description
feat(rme): read DRAM information from FVP DTB
feat(rme): s

Merge changes I1b092bc1,Ifc2461b4,I5176caa5 into integration

* changes:
docs(rme): update RMM-EL3 Boot Manifest structure description
feat(rme): read DRAM information from FVP DTB
feat(rme): set DRAM information in Boot Manifest platform data

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feat(versal-net): add jtag dcc support

Add support for JTAG Debug Communication Channel(DCC), using the dcc
console driver, for Versal NET platform.
UART0/UART1 is not configured when the JTAG DCC i

feat(versal-net): add jtag dcc support

Add support for JTAG Debug Communication Channel(DCC), using the dcc
console driver, for Versal NET platform.
UART0/UART1 is not configured when the JTAG DCC is used as console for
the platform.
Though DCC is not using any UART, VERSAL_NET_UART_BASE needs
to be defined in the platform code. If its not defined, build errors
are observed.
Now VERSAL_NET_UART_BASE by default points to UART0 base.
Check for valid console(pl011, pl011_0, pl011_1, dcc) is
being done in the platform makefile, the error condition in
setting the value of VERSAL_NET_UART_BASE is redundant, thus the error
message is removed from the code.

Change-Id: I1085433055abea13526230cff4d4183ff7a01477
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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feat(optee): add loading OP-TEE image via an SMC

This adds the ability to load the OP-TEE image via an SMC called from
non-secure userspace rather than loading it during boot. This should
only be ut

feat(optee): add loading OP-TEE image via an SMC

This adds the ability to load the OP-TEE image via an SMC called from
non-secure userspace rather than loading it during boot. This should
only be utilized on platforms that can ensure security is maintained up
until the point the SMC is invoked as it breaks the normal barrier
between the secure and non-secure world.

Signed-off-by: Jeffrey Kardatzke <jkardatzke@google.com>
Change-Id: I21cfa9699617c493fa4190f01d1cbb714e7449cc

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docs(rme): update RMM-EL3 Boot Manifest structure description

This patch updates description of RMM-EL3 Boot Manifest
structure and its corresponding diagram and tables with DRAM
layout data.

Signe

docs(rme): update RMM-EL3 Boot Manifest structure description

This patch updates description of RMM-EL3 Boot Manifest
structure and its corresponding diagram and tables with DRAM
layout data.

Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: I1b092bc1ad5f1c7909d25c1a0dc89c2b210ada27

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Merge "docs(measured-boot): fix few typos" into integration

docs(measured-boot): fix few typos

Fixed few typos in the measured boot POC document.

Change-Id: I122c069bbde51febed12c54e2c4a4985b009ef5f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

Merge "fix(cpus): workaround for Cortex-A78C erratum 2772121" into integration

Merge "fix(cpus): workaround for Cortex-A510 erratum 2684597" into integration

docs(spm): add other-s-interrupts-action field to sp manifest

Also, the `run-time-model` field is removed from SP manifest binding
as it is not supported by Hafnium(SPMC).

Change-Id: Id8a91b2608791

docs(spm): add other-s-interrupts-action field to sp manifest

Also, the `run-time-model` field is removed from SP manifest binding
as it is not supported by Hafnium(SPMC).

Change-Id: Id8a91b2608791667e6285b3c5b879ec84612149d
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge "docs(rme): improve OOB instruction for RME" into integration

docs(rme): improve OOB instruction for RME

This patch reworks the existing OOB instructions for RME enabled
TF-A.

Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: Icaeaf48c7061feaad4b1bb

docs(rme): improve OOB instruction for RME

This patch reworks the existing OOB instructions for RME enabled
TF-A.

Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: Icaeaf48c7061feaad4b1bb92388954694705e45c

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fix(cpus): workaround for Cortex-A510 erratum 2684597

Cortex-A510 erratum 2684597 is a Cat B erratum that applies to revisions
r0p0, r0p1, r0p2, r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3. The
w

fix(cpus): workaround for Cortex-A510 erratum 2684597

Cortex-A510 erratum 2684597 is a Cat B erratum that applies to revisions
r0p0, r0p1, r0p2, r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3. The
workaround is to execute a TSB CSYNC and DSB before executing WFI for
power down.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1873361/latest
https://developer.arm.com/documentation/SDEN1873351/latest

Change-Id: Ic0b24b600bc013eb59c797401fbdc9bda8058d6d
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge "docs: change security advisories notification channel" into integration

Merge changes from topic "srm/errata" into integration

* changes:
fix(cpus): workaround for Neoverse V1 errata 2779461
fix(cpus): workaround for Cortex-A78 erratum 2779479

fix(cpus): workaround for Neoverse V1 errata 2779461

Neoverse V1 erratum 2779461 is a Cat B erratum that applies to
all revisions <=r1p2 and is still open.

The workaround sets CPUACTLR3_EL1[47] bit

fix(cpus): workaround for Neoverse V1 errata 2779461

Neoverse V1 erratum 2779461 is a Cat B erratum that applies to
all revisions <=r1p2 and is still open.

The workaround sets CPUACTLR3_EL1[47] bit to 1. Setting this
bit might have a small impact on power and negligible impact
on performance.

SDEN documentation:https://developer.arm.com/documentation/SDEN1401781/latest

Change-Id: I367cda1779684638063d7292fda20ca6734e6f10
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>

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fix(cpus): workaround for Cortex-A78 erratum 2779479

Cortex-A78 erratum 2779479 is a Cat B erratum that applies to
all revisions <= r1p2 and is still open.

The workaround is to set the CPUACTLR3_EL

fix(cpus): workaround for Cortex-A78 erratum 2779479

Cortex-A78 erratum 2779479 is a Cat B erratum that applies to
all revisions <= r1p2 and is still open.

The workaround is to set the CPUACTLR3_EL1[47] bit to 1. Setting this
bit might have a small impact on power and negligible impact
on performance.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1401784/latest

Change-Id: I3779fd1eff3017c5961ffa101b357918070b3b36
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>

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fix(cpus): workaround for Cortex-A78C erratum 2772121

Cortex-A78C erratum 2772121 is a Cat B erratum that applies to
all revisions <=r0p2 and is still open. The workaround is to
insert a dsb before

fix(cpus): workaround for Cortex-A78C erratum 2772121

Cortex-A78C erratum 2772121 is a Cat B erratum that applies to
all revisions <=r0p2 and is still open. The workaround is to
insert a dsb before the isb in the power down sequence.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1707916/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I0e190dabffc20c4d3b9b98d1abeb50f308b80bb9

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Merge changes from topic "deprecate_io_drivers" into integration

* changes:
refactor(st): remove unused io_mmc driver
docs: deprecate io_dummy driver