| 748749a8 | 24-Aug-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "fix(errata): workaround for Cortex-A510 erratum 2371937" into integration |
| ac2605e6 | 24-Aug-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "fix(errata): workaround for Cortex-A78C erratum 2395411" into integration |
| 4b6f0026 | 19-Jul-2022 |
Akram Ahmad <Akram.Ahmad@arm.com> |
fix(errata): workaround for Cortex-A78C erratum 2395411
Cortex-A78C erratum 2395411 is a Cat B erratum that affects
revisions r0p1 and r0p2, and is currently open. The workaround
is to set CPUACTLR2
fix(errata): workaround for Cortex-A78C erratum 2395411
Cortex-A78C erratum 2395411 is a Cat B erratum that affects
revisions r0p1 and r0p2, and is currently open. The workaround
is to set CPUACTLR2_EL1[40] to 1, which will disable folding
of demand requests into older prefetches with L2 miss requests
outstanding.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2004089/latest
Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I4f0fb278ac20a2eb4dd7e4efd1b1246dd85e48c4
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| a67c1b1b | 22-Jul-2022 |
Akram Ahmad <Akram.Ahmad@arm.com> |
fix(errata): workaround for Cortex-A510 erratum 2371937
Cortex-A510 erratum 2371937 is a Cat B erratum that applies
to revisions r0p0, r0p1, r0p2, r0p3, r1p0, and r1p1. It is
fixed in r1p2. The work
fix(errata): workaround for Cortex-A510 erratum 2371937
Cortex-A510 erratum 2371937 is a Cat B erratum that applies
to revisions r0p0, r0p1, r0p2, r0p3, r1p0, and r1p1. It is
fixed in r1p2. The workaround is to set the ATOM field of
CPUECTLR_EL1 (bits [40:38]) to 0b010, which will force all
cacheable atomic operations to be executed near.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1873351/latest
https://developer.arm.com/documentation/SDEN1873361/latest
Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: Ia219a609a3397e39631de65831ecff8a3cd1227e
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| 3280e5e6 | 21-Jul-2022 |
Akram Ahmad <Akram.Ahmad@arm.com> |
fix(errata): workaround for Cortex-A710 erratum 2147715
Cortex-A710 erratum 2147715 is a Cat B erratum that applies
to revision r2p0 of the CPU, and is fixed in r2p1. The work-
around is to set CPUA
fix(errata): workaround for Cortex-A710 erratum 2147715
Cortex-A710 erratum 2147715 is a Cat B erratum that applies
to revision r2p0 of the CPU, and is fixed in r2p1. The work-
around is to set CPUACTLR_EL1[22]=1. Setting this will cause
the CFP instruction to invalidate all branch predictor resources
regardless of the context.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I94771bc1fc9b65a0c17d75200ec2b1df8a3279c6
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|
| 3a416588 | 18-Aug-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "feat(rng-trap): add EL3 support for FEAT_RNG_TRAP" into integration |
| ff86e0b4 | 12-Jul-2022 |
Juan Pablo Conde <juanpablo.conde@arm.com> |
feat(rng-trap): add EL3 support for FEAT_RNG_TRAP
FEAT_RNG_TRAP introduces support for EL3 trapping of reads of the
RNDR and RNDRRS registers, which is enabled by setting the
SCR_EL3.TRNDR bit. This
feat(rng-trap): add EL3 support for FEAT_RNG_TRAP
FEAT_RNG_TRAP introduces support for EL3 trapping of reads of the
RNDR and RNDRRS registers, which is enabled by setting the
SCR_EL3.TRNDR bit. This patch adds a new build flag
ENABLE_FEAT_RNG_TRAP that enables the feature.
This feature is supported only in AArch64 state from Armv8.5 onwards.
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: Ia9f17aef3444d3822bf03809036a1f668c9f2d89
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| e6602d4b | 18-Jul-2022 |
Akram Ahmad <Akram.Ahmad@arm.com> |
fix(errata): workaround for Neoverse-N2 erratum 2376738
Neoverse-N2 erratum 2376738 is a Cat B erratum that applies
to revision r0p0 of the CPU. It is fixed in r0p1. The workaround
is to set CPUACTL
fix(errata): workaround for Neoverse-N2 erratum 2376738
Neoverse-N2 erratum 2376738 is a Cat B erratum that applies
to revision r0p0 of the CPU. It is fixed in r0p1. The workaround
is to set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to
behave like PLD/PRFM LD and not cause invalidations to other
PE caches.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I4ad4434f9b7210244e67046d9657d218857dced5
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|
| b48cd784 | 09-Aug-2022 |
Pali Rohár <pali@kernel.org> |
docs(marvell): document UART image downloading
For A3K there are two different tools for booting Armada37x0 platform
over UART, one from Marvell and second from CZ.NIC. For A8K there is
just one my
docs(marvell): document UART image downloading
For A3K there are two different tools for booting Armada37x0 platform
over UART, one from Marvell and second from CZ.NIC. For A8K there is
just one my own mvebu64boot tool.
Add documentation how to build these tools and how to download TF-A
image over UART to boot TF-A without flashing it to non-volatile
storage.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ifa03584010a9c40496a34e6d5b9f3b78cb2cc89b
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|
| 6a502227 | 11-Aug-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(errata): workaround for Neoverse-V1 erratum 1618635" into integration |
| 1631f9c7 | 09-Aug-2022 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "feat(sve): support full SVE vector length" into integration |
| 89e4cea1 | 24-Jun-2022 |
Arthur She <arthur.she@linaro.org> |
docs(juno): fix broken link
The URL of the Juno Getting Started Guide has been changed.
Fix the broken link.
Signed-off-by: Arthur She <arthur.she@linaro.org>
Change-Id: I55697f2f1f787c32d1ea7dfcf9
docs(juno): fix broken link
The URL of the Juno Getting Started Guide has been changed.
Fix the broken link.
Signed-off-by: Arthur She <arthur.she@linaro.org>
Change-Id: I55697f2f1f787c32d1ea7dfcf9eda619906cdb5d
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|
| 14a6fed5 | 28-Feb-2022 |
Juan Pablo Conde <juanpablo.conde@arm.com> |
fix(errata): workaround for Neoverse-V1 erratum 1618635
Neoverse-V1 erratum 1618635 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.
The workaround is done through the instruct
fix(errata): workaround for Neoverse-V1 erratum 1618635
Neoverse-V1 erratum 1618635 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.
The workaround is done through the instruction patching
mechanism, which is performed by a write sequence of
IMPLEMENTATION DEFINED registers.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401781/latest/
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: I53e406735cd3a2a930fdc72ebce3bbed97100168
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|
| 09acc421 | 25-Jul-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(tc): introduce TC2 platform" into integration |
| a3190343 | 25-Jul-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge "docs(maintainers): switch emails from Xilinx to AMD" into integration |
| 094b8463 | 25-Jul-2022 |
Michal Simek <michal.simek@amd.com> |
docs(maintainers): switch emails from Xilinx to AMD
Switch emails from Xilinx to AMD after acquisition.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I5d126dc49e53f2735bb7e103f8f883
docs(maintainers): switch emails from Xilinx to AMD
Switch emails from Xilinx to AMD after acquisition.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I5d126dc49e53f2735bb7e103f8f883a9474206fc
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|
| eebd2c3f | 04-Apr-2022 |
Rupinderjit Singh <rupinderjit.singh@arm.com> |
feat(tc): introduce TC2 platform
Added a platform support to use tc2 specific CPU cores.
Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Change-Id: Ib76d440e358e9bd1cf80aec5b8591f7a6e4
feat(tc): introduce TC2 platform
Added a platform support to use tc2 specific CPU cores.
Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Change-Id: Ib76d440e358e9bd1cf80aec5b8591f7a6e47ecbd
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|
| 3f9d5c24 | 22-Jul-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(doc): document missing RMM-EL3 runtime services" into integration |
| c1d7585d | 21-Jul-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(errata): workaround for Cortex-X2 erratum 2371105" into integration |
| bc0f84de | 12-Jul-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(errata): workaround for Cortex-X2 erratum 2371105
Cortex-X2 erratum 2371105 is a cat B erratum that applies to
revisions r0p0 - r2p0 and is fixed in r2p1. The workaround is to
set bit[40] of CPU
fix(errata): workaround for Cortex-X2 erratum 2371105
Cortex-X2 erratum 2371105 is a cat B erratum that applies to
revisions r0p0 - r2p0 and is fixed in r2p1. The workaround is to
set bit[40] of CPUACTLR2_EL1 to disable folding of demand requests
into older prefetches with L2 miss requests outstanding.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ib4f0caac36e1ecf049871acdea45526b394b7bad
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|
| 486ebd68 | 21-Jul-2022 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge "fix(errata): workaround for Cortex A78C erratum 2242638" into integration |
| e50fedbc | 04-Jul-2022 |
Javier Almansa Sobrino <javier.almansasobrino@arm.com> |
fix(doc): document missing RMM-EL3 runtime services
This patch adds documentation for the missing RMM-EL3
runtime services:
* RMM_RMI_REQ_COMPLETE
* RMM_GTSI_DELEGATE
* RMM_GTSI_UNDELEGATE
This pa
fix(doc): document missing RMM-EL3 runtime services
This patch adds documentation for the missing RMM-EL3
runtime services:
* RMM_RMI_REQ_COMPLETE
* RMM_GTSI_DELEGATE
* RMM_GTSI_UNDELEGATE
This patch also fixes a couple of minor bugs on return codes
for delegate/undelegate internal APIs.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: Ic721005e7851e838eebaee7865ba78fadc3309e4
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|
| 6be1aa7e | 20-Jul-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(errata): workaround for Cortex-A710 erratum 2371105" into integration |
| 3220f05e | 12-Jul-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(errata): workaround for Cortex-A710 erratum 2371105
Cortex-A710 erratum 2371105 is a cat B erratum that applies to
revisions r0p0 - r2p0 and is fixed in r2p1. The workaround is to
set bit[40] of
fix(errata): workaround for Cortex-A710 erratum 2371105
Cortex-A710 erratum 2371105 is a cat B erratum that applies to
revisions r0p0 - r2p0 and is fixed in r2p1. The workaround is to
set bit[40] of CPUACTLR2_EL1 to disable folding of demand requests
into older prefetches with L2 miss requests outstanding.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I342b095b66f808bd6c066c20c581df5341bb7c2c
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|
| 6979f47f | 15-Jul-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(errata): workaround for Cortex A78C erratum 2242638
Cortex A78C erratum 2242638 is a Cat B erratum which applies to
revisions r0p1, r0p2 and is still open. The workaround is to apply
a CPU imple
fix(errata): workaround for Cortex A78C erratum 2242638
Cortex A78C erratum 2242638 is a Cat B erratum which applies to
revisions r0p1, r0p2 and is still open. The workaround is to apply
a CPU implementation specific specific patch sequence.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2004089/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I35d385245a04a39b87be71c1a42312f75e1152e5
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|