| 48fb9315 | 06-Mar-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "docs(spm): add other-s-interrupts-action field to sp manifest" into integration |
| c52a142b | 27-Feb-2023 |
Akshay Belsare <akshay.belsare@amd.com> |
fix(zynqmp): conditional reservation of memory in DTB
When the TF-A is placed in DDR memory range, the DDR memory range is
getting explicitly reserved in the default device tree by TF-A.
This create
fix(zynqmp): conditional reservation of memory in DTB
When the TF-A is placed in DDR memory range, the DDR memory range is
getting explicitly reserved in the default device tree by TF-A.
This creates an error condition in the use case where Device tree is
not present or it is present at a different location.
To fix this, a new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is
introduced. The TF-A will reserve the DDR memory only when a valid
DTB address is provided to XILINX_OF_BOARD_DTB_ADDR during build.
Now the user has options, either manually reserve the desired
DDR address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.
Change-Id: I846fa373ba9f7c984eda3a55ccaaa622082cad81
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
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| dc2b8e80 | 23-Feb-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge changes from topic "panic_cleanup" into integration
* changes:
refactor(bl31): use elx_panic for sysreg_handler64
refactor(aarch64): rename do_panic and el3_panic
refactor(aarch64): remo
Merge changes from topic "panic_cleanup" into integration
* changes:
refactor(bl31): use elx_panic for sysreg_handler64
refactor(aarch64): rename do_panic and el3_panic
refactor(aarch64): remove weak links to el3_panic
refactor(aarch64): refactor usage of elx_panic
refactor(aarch64): cleanup HANDLE_EA_EL3_FIRST_NS usage
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| 17d07a55 | 21-Feb-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
refactor(bl31): use elx_panic for sysreg_handler64
When we reach sysreg_handler64 from any trap handling we are entering
this path from lower EL and thus we should be calling lower_el_panic
reportin
refactor(bl31): use elx_panic for sysreg_handler64
When we reach sysreg_handler64 from any trap handling we are entering
this path from lower EL and thus we should be calling lower_el_panic
reporting mechanism to print panic report.
Make report_elx_panic available through assembly func elx_panic which
could be used for reporting any lower_el_panic.
Change-Id: Ieb260cf20ea327a59db84198b2c6a6bfc9ca9537
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| 83a67987 | 22-Feb-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "docs: add interrupts-target field to sp manifest" into integration |
| 338dbe2f | 22-Feb-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I51c13c52,I3358c51e into integration
* changes:
build: always prefix section names with `.`
build: communicate correct page size to linker |
| ba12668a | 22-Feb-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(gicv3): enlarge the range for intr_num of structure interrupt_prop_t" into integration |
| bd62ce98 | 16-Jan-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
refactor(aarch64): rename do_panic and el3_panic
Current panic call invokes do_panic which calls el3_panic, but now panic
handles only panic from EL3 anid clear separation to use lower_el_panic()
wh
refactor(aarch64): rename do_panic and el3_panic
Current panic call invokes do_panic which calls el3_panic, but now panic
handles only panic from EL3 anid clear separation to use lower_el_panic()
which handles panic from lower ELs.
So now we can remove do_panic and just call el3_panic for all panics.
Change-Id: I739c69271b9fb15c1176050877a9b0c0394dc739
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| 45d7c51a | 20-Feb-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs(drtm): mention DRTM_SUPPORT as an experimental build option
In spite of the fact that makefile [1] indicates that DRTM_SUPPORT is
an experimental feature, it is better to mention the same in th
docs(drtm): mention DRTM_SUPPORT as an experimental build option
In spite of the fact that makefile [1] indicates that DRTM_SUPPORT is
an experimental feature, it is better to mention the same in the
documentation of the build option as well.
[1]:
https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/Makefile#n897
Change-Id: Ibfa328ec8ed685ce715d144d979ba37e4f49f82e
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| da04341e | 14-Feb-2023 |
Chris Kay <chris.kay@arm.com> |
build: always prefix section names with `.`
Some of our specialized sections are not prefixed with the conventional
period. The compiler uses input section names to derive certain other
section name
build: always prefix section names with `.`
Some of our specialized sections are not prefixed with the conventional
period. The compiler uses input section names to derive certain other
section names (e.g. `.rela.text`, `.relacpu_ops`), and these can be
difficult to select in linker scripts when there is a lack of a
delimiter.
This change introduces the period prefix to all specialized section
names.
BREAKING-CHANGE: All input and output linker section names have been
prefixed with the period character, e.g. `cpu_ops` -> `.cpu_ops`.
Change-Id: I51c13c5266d5975fbd944ef4961328e72f82fc1c
Signed-off-by: Chris Kay <chris.kay@arm.com>
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| d2d71e2e | 20-Feb-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "fix(docs): add few missed links for Security Advisories" into integration |
| 9c571fb0 | 17-Feb-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge "feat(zynqmp): add support for custom sip service" into integration |
| 43f3a9c4 | 16-Feb-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
fix(docs): add few missed links for Security Advisories
Added few missed links for Security Advisories.
Change-Id: I9cab72b70a518273cbb1a291142f452198427127
Signed-off-by: Manish V Badarkhe <Manish
fix(docs): add few missed links for Security Advisories
Added few missed links for Security Advisories.
Change-Id: I9cab72b70a518273cbb1a291142f452198427127
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 496d7081 | 15-Feb-2023 |
Amit Nagal <amit.nagal@amd.com> |
feat(zynqmp): add support for custom sip service
Add support for custom sip service.
Bare minimum implementation for custom_smc_handler is provided
by platform. Actual definition for custom_smc_hand
feat(zynqmp): add support for custom sip service
Add support for custom sip service.
Bare minimum implementation for custom_smc_handler is provided
by platform. Actual definition for custom_smc_handler will be provided
by custom pkg.
This feature is going to be used by external libraries. For example
for checking it's status.
The similar approach is also used by qti/{sc7180,sc7280} platforms
by providing a way to select QTISECLIB_PATH.
This code is providing a generic way how to wire any code
via custom $(CUSTOM_PKG_PATH)/custom_pkg.mk makefile with also an
option to wire custom SMC. SMC functionality depends on "package".
Change-Id: Icedffd582f76f89fc399b0bb2e05cdaee9b743a0
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
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| 2537f072 | 15-Feb-2023 |
Akshay Belsare <akshay.belsare@amd.com> |
fix(zynqmp): with DEBUG=1 move bl31 to DDR range
Due to size constraints in OCM memory range keeping the bl31 with
DEBUG=1 overlaps with the memory range from other Firmware thus
affecting the bootf
fix(zynqmp): with DEBUG=1 move bl31 to DDR range
Due to size constraints in OCM memory range keeping the bl31 with
DEBUG=1 overlaps with the memory range from other Firmware thus
affecting the bootflow on target.
bl31 binary can not be placed in OCM memory range when built with
DEBUG=1.
With DEBUG=1, by default bl31 is moved to DDR memory range
0x1000-0x7FFFF.
The user can provide a custom DDR memory range during build time using
the build parameters ZYNQMP_ATF_MEM_BASE and ZYNQMP_ATF_MEM_SIZE.
Change-Id: I167d5eadbae7c6d3ec9b32f494b0b1a819bea5b0
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
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| 5a77fd3b | 15-Feb-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "docs(qemu): delineate flash based boot method" into integration |
| 23af5965 | 14-Feb-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "bk/python_dependencies" into integration
* changes:
build(docs): update Python dependencies
fix(docs): make required compiler version == rather than >=
fix(deps): add
Merge changes from topic "bk/python_dependencies" into integration
* changes:
build(docs): update Python dependencies
fix(docs): make required compiler version == rather than >=
fix(deps): add missing aeabi_memset.S
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| 9d1a325b | 14-Feb-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "docs: fix broken Juno links" into integration |
| 0cbcccc0 | 13-Feb-2023 |
Harrison Mutai <harrison.mutai@arm.com> |
docs: fix broken Juno links
Certain links to Juno documentation point to a location that were
removed at some point, or are unused. Fix links to point to the latest
available version on Arm's public
docs: fix broken Juno links
Certain links to Juno documentation point to a location that were
removed at some point, or are unused. Fix links to point to the latest
available version on Arm's public documentation site, and remove those
that are no longer being used.
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Change-Id: I59202767db8834e9c302b2826f3faee47d3a5edd
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| b7c37e4a | 09-Jan-2023 |
Boyan Karatotev <boyan.karatotev@arm.com> |
build(docs): update Python dependencies
Update the python dependencies for building the project's Sphinx
documentation. Sphinx plugins are updated to the latest version, while
Sphinx itself is only
build(docs): update Python dependencies
Update the python dependencies for building the project's Sphinx
documentation. Sphinx plugins are updated to the latest version, while
Sphinx itself is only updated to 5.3.0 (latest 5.x.x revision) due to
sphinx-rtd-theme not supporting any higher (both require incompatible
versions of docutils). Myst-parser is also updated to the latest version
to prevent a docutils clash as well.
The effect of this is to bump certifi to version 2022.12.7 and wheel to
0.38.4 as suggested by dependabot.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I0ced5b127494255ce01aa7f51665bfcba161d135
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| 415195c0 | 09-Feb-2023 |
Boyan Karatotev <boyan.karatotev@arm.com> |
fix(docs): make required compiler version == rather than >=
TF-A carries its own compiler-rt so higher versions of the compilers may
not necessarily work. Because TF-A is only tested on the specifie
fix(docs): make required compiler version == rather than >=
TF-A carries its own compiler-rt so higher versions of the compilers may
not necessarily work. Because TF-A is only tested on the specified
versions in the CI, any breakage remains unknown. Update the
prerequisites guide to make it more apparent that this is the case.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ia5da9c5ff505ead99f579f3f5fbe3a480d697c1d
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| c8a95567 | 13-Feb-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "docs: add Runtime Security Subsystem (RSS) documentation" into integration |
| eea607cb | 13-Oct-2022 |
Tamas Ban <tamas.ban@arm.com> |
docs: add Runtime Security Subsystem (RSS) documentation
Describe:
- RSS-AP communication
- RSS runtime services
- Measured boot
- Delegated Attestation
Signed-off-by: Tamas Ban <tamas.ban@
docs: add Runtime Security Subsystem (RSS) documentation
Describe:
- RSS-AP communication
- RSS runtime services
- Measured boot
- Delegated Attestation
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Iaef93361a09355a1edaabcc0c59126e006ad251a
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| a13b4cd7 | 10-Feb-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge "fix(optee): address late comments and fix bad rc" into integration |
| af4fee04 | 10-Feb-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "mb/tos-fw-config-load-refactor" into integration
* changes:
feat(spmd): map SPMC manifest region as EL3_PAS
feat(fvp): update device tree with load addresses of TOS_FW
Merge changes from topic "mb/tos-fw-config-load-refactor" into integration
* changes:
feat(spmd): map SPMC manifest region as EL3_PAS
feat(fvp): update device tree with load addresses of TOS_FW config
refactor(fvp): rename the DTB info structure member
feat(fconf): rename 'ns-load-address' to 'secondary-load-address'
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