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4181ebb9 |
| 08-Apr-2025 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "fix(plat): remove fvp_r" into integration
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2cadf21b |
| 12-Mar-2025 |
Boyan Karatotev <boyan.karatotev@arm.com> |
fix(plat): remove fvp_r
The platform has not been maintained for some years and is generally broken. Remove it to avoid confusion.
Change-Id: I93d832d51e114689ec79969af5d96071a03f4a88 Signed-off-by
fix(plat): remove fvp_r
The platform has not been maintained for some years and is generally broken. Remove it to avoid confusion.
Change-Id: I93d832d51e114689ec79969af5d96071a03f4a88 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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26467bf3 |
| 01-Oct-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "rd1ae-upstream" into integration
* changes: docs(rd1ae): add RD-1 AE documentation feat(rd1ae): enabling Trusted Board Boot(TBB) for RD-1 AE feat(rd1ae): introduce BL
Merge changes from topic "rd1ae-upstream" into integration
* changes: docs(rd1ae): add RD-1 AE documentation feat(rd1ae): enabling Trusted Board Boot(TBB) for RD-1 AE feat(rd1ae): introduce BL31 for RD-1 AE platform feat(rd1ae): add device tree files feat(rd1ae): introduce Arm RD-1 AE platform build(bl2): enable check for bl2 base overflow assert feat(arm): add support for loading CONFIG from BL2
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53e75cfa |
| 16-Apr-2024 |
Divin Raj <divin.raj@arm.com> |
docs(rd1ae): add RD-1 AE documentation
Documenting RD-1 AE features, boot sequence, and build procedure.
Signed-off-by: Divin Raj <divin.raj@arm.com> Change-Id: Ie93438931e9ead42a2a6dd2d752d37bc06f
docs(rd1ae): add RD-1 AE documentation
Documenting RD-1 AE features, boot sequence, and build procedure.
Signed-off-by: Divin Raj <divin.raj@arm.com> Change-Id: Ie93438931e9ead42a2a6dd2d752d37bc06fa2e32
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24872370 |
| 15-Feb-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "ea/corstone1000" into integration
* changes: feat(corstone1000): identify bank to load fip fix(corstone1000): change base address of FIP in the flash feat(corstone100
Merge changes from topic "ea/corstone1000" into integration
* changes: feat(corstone1000): identify bank to load fip fix(corstone1000): change base address of FIP in the flash feat(corstone1000): implement platform specific psci reset feat(corstone1000): made changes to accommodate 3MB for optee build(corstone1000): rename diphda to corstone1000
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0260eb0d |
| 19-Jan-2022 |
Vishnu Banavath <vishnu.banavath@arm.com> |
build(corstone1000): rename diphda to corstone1000
diphda platform is now being renamed to corstone1000. These changes are to replace all the instances and traces of diphda corstone1000.
Change-Id
build(corstone1000): rename diphda to corstone1000
diphda platform is now being renamed to corstone1000. These changes are to replace all the instances and traces of diphda corstone1000.
Change-Id: I330f3a112d232b99b4721b6bf0236253b068dbba Signed-off-by: Arpita S.K <Arpita.S.K@arm.com> Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
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a07c94b4 |
| 30-Sep-2021 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "gm/reviewCI" into integration
* changes: docs: armv8-R aarch64 fvp_r documentation fvp_r: load, auth, and transfer from BL1 to BL33 chore: fvp_r: Initial No-EL3 and
Merge changes from topic "gm/reviewCI" into integration
* changes: docs: armv8-R aarch64 fvp_r documentation fvp_r: load, auth, and transfer from BL1 to BL33 chore: fvp_r: Initial No-EL3 and MPU Implementation fvp_r: initial platform port for fvp_r
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cd12b195 |
| 13-May-2021 |
laurenw-arm <lauren.wehrmeister@arm.com> |
docs: armv8-R aarch64 fvp_r documentation
Documenting armv8-R aarch64 fvp_r features, boot sequence, and build procedure.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I
docs: armv8-R aarch64 fvp_r documentation
Documenting armv8-R aarch64 fvp_r features, boot sequence, and build procedure.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: If75d59acdf0f8a61cea6187967a4c35af2f31c98
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ae5cfc5f |
| 11-Aug-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "feat(plat/arm): Introduce TC1 platform" into integration
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6ec0c65b |
| 09-Apr-2021 |
Usama Arif <usama.arif@arm.com> |
feat(plat/arm): Introduce TC1 platform
This renames tc0 platform folder and files to tc, and introduces TARGET_PLATFORM variable to account for the differences between TC0 and TC1.
Signed-off-by: U
feat(plat/arm): Introduce TC1 platform
This renames tc0 platform folder and files to tc, and introduces TARGET_PLATFORM variable to account for the differences between TC0 and TC1.
Signed-off-by: Usama Arif <usama.arif@arm.com> Change-Id: I5b4a83f3453afd12542267091b3edab4c139c5cd
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d55d8309 |
| 23-Jul-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "diphda" into integration
* changes: feat: disabling non volatile counters in diphda feat: adding the diphda platform
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bf3ce993 |
| 21-Apr-2021 |
Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> |
feat: adding the diphda platform
This commit enables trusted-firmware-a with Trusted Board Boot support for the Diphda 64-bit platform.
Diphda uses a FIP image located in the flash. The FIP contain
feat: adding the diphda platform
This commit enables trusted-firmware-a with Trusted Board Boot support for the Diphda 64-bit platform.
Diphda uses a FIP image located in the flash. The FIP contains the following components:
- BL2 - BL31 - BL32 - BL32 SPMC manifest - BL33 - The TBB certificates
The board boot relies on CoT (chain of trust). The trusted-firmware-a BL2 is extracted from the FIP and verified by the Secure Enclave processor. BL2 verification relies on the signature area at the beginning of the BL2 image. This area is needed by the SecureEnclave bootloader.
Then, the application processor is released from reset and starts by executing BL2.
BL2 performs the actions described in the trusted-firmware-a TBB design document.
Signed-off-by: Rui Miguel Silva <rui.silva@arm.com> Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> Change-Id: Iddb1cb9c2a0324a9635e23821c210ac81dfc305d
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950e37d8 |
| 02-Oct-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "morello: Add Morello platform documentation" into integration
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8445253e |
| 01-Oct-2020 |
Chandni Cherukuri <chandni.cherukuri@arm.com> |
morello: Add Morello platform documentation
Morello platform has a SCP which brings the primary Rainier CPU out of reset which starts executing at BL31.
This patch provides documentation support fo
morello: Add Morello platform documentation
Morello platform has a SCP which brings the primary Rainier CPU out of reset which starts executing at BL31.
This patch provides documentation support for Morello platform.
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com> Change-Id: I38f596668e2b14862d543fabc04549ff34bfb8a2
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2173b3e0 |
| 30-Sep-2020 |
André Przywara <andre.przywara@arm.com> |
Merge changes from topic "fpga_generic" into integration
* changes: arm_fpga: Add platform documentation arm_fpga: Add post-build linker script arm_fpga: Add ROM trampoline arm_fpga: Add dev
Merge changes from topic "fpga_generic" into integration
* changes: arm_fpga: Add platform documentation arm_fpga: Add post-build linker script arm_fpga: Add ROM trampoline arm_fpga: Add devicetree file arm_fpga: Remove SPE PMU DT node if SPE is not available arm_fpga: Adjust GICR size in DT to match number of cores fdt: Add function to adjust GICv3 redistributor size drivers: arm: gicv3: Allow detecting number of cores
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a6c07e0d |
| 27-Aug-2020 |
Andre Przywara <andre.przywara@arm.com> |
arm_fpga: Add platform documentation
As the Arm Ltd. FPGA port is now working for all existing images, add some documentation file.
Change-Id: I9e2c532ed15bbc121bb54b3dfc1bdfee8f1443a6 Signed-off-b
arm_fpga: Add platform documentation
As the Arm Ltd. FPGA port is now working for all existing images, add some documentation file.
Change-Id: I9e2c532ed15bbc121bb54b3dfc1bdfee8f1443a6 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| #
2fe7d18b |
| 27-May-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "plat/arm: Introduce TC0 platform" into integration
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f5c58af6 |
| 17-Apr-2020 |
Usama Arif <usama.arif@arm.com> |
plat/arm: Introduce TC0 platform
This patch adds support for Total Compute (TC0) platform. It is an initial port and additional features are expected to be added later.
TC0 has a SCP which brings t
plat/arm: Introduce TC0 platform
This patch adds support for Total Compute (TC0) platform. It is an initial port and additional features are expected to be added later.
TC0 has a SCP which brings the primary Cortex-A out of reset which starts executing BL1. TF-A optionally authenticates the SCP ram-fw available in FIP and makes it available for SCP to copy.
Some of the major features included and tested in this platform port include TBBR, PSCI, MHUv2 and DVFS.
Change-Id: I1675e9d200ca7687c215009eef483d9b3ee764ef Signed-off-by: Usama Arif <usama.arif@arm.com>
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f325f9ce |
| 27-Nov-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "doc: Split the User Guide into multiple files" into integration
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43f35ef5 |
| 29-May-2019 |
Paul Beesley <paul.beesley@arm.com> |
doc: Split the User Guide into multiple files
The User Guide document has grown organically over time and now covers a wide range of topics, making it difficult to skim read and extract information
doc: Split the User Guide into multiple files
The User Guide document has grown organically over time and now covers a wide range of topics, making it difficult to skim read and extract information from. Currently, it covers these topics and maybe a couple more:
- Requirements (hardware, tools, libs) - Checking out the repo - Basic build instructions - A comprehensive list of build flags - FIP packaging - Building specifically for Juno - Firmware update images - EL3 payloads - Preloaded BL33 boot flow - Running on FVPs - Running on Juno
I have separated these out into a few groups that become new documents. Broadly speaking, build instructions for the tools, for TF-A generally, and for specific scenarios are separated. Content relating to specific platforms (Juno and the FVPs are Arm-specific platforms, essentially) has been moved into the documentation that is specific to those platforms, under docs/plat/arm.
Change-Id: Ica87c52d8cd4f577332be0b0738998ea3ba3bbec Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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