Merge changes from topic "xl/cortex_a510-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A510 erratum 2002389
fix(cpus): workaround for Cortex-A510 erratum 1976290
fix(cpu

Merge changes from topic "xl/cortex_a510-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A510 erratum 2002389
fix(cpus): workaround for Cortex-A510 erratum 1976290
fix(cpus): workaround for Cortex-A510 erratum 2028010
fix(cpus): workaround for Cortex-A510 erratum 2027318
fix(cpus): workaround for Cortex-A510 erratum 1975068
fix(cpus): workaround for Cortex-A510 erratum 1966377
fix(cpus): workaround for Cortex-A510 erratum 1952872
fix(cpus): workaround for Cortex-A510 erratum 1942494
fix(cpus): workaround for Cortex-A510 erratum 1937669
fix(cpus): workaround for Cortex-A510 erratum 1910738

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fix(cpus): workaround for Cortex-A510 erratum 2002389

Cortex-A510 erratum 2002389 is a Cat B erratum that applies to
revisions r0p0, r0p1. It is fixed in r0p2.

If a workaround is required this erra

fix(cpus): workaround for Cortex-A510 erratum 2002389

Cortex-A510 erratum 2002389 is a Cat B erratum that applies to
revisions r0p0, r0p1. It is fixed in r0p2.

If a workaround is required this erratum can be avoided by setting
IMP_CPUACTLR_EL1[3] = 1. This is expected to impact performance by
around 1.3%.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1873351/latest

Change-Id: I799b40583146fdc62515a94f9c2202ef8c79682d
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A510 erratum 1976290

Cortex-A510 erratum 1976290 is a Cat B erratum that applies to
revision r0p0. It is fixed in r0p1.

This erratum can be avoided by setting IMP_C

fix(cpus): workaround for Cortex-A510 erratum 1976290

Cortex-A510 erratum 1976290 is a Cat B erratum that applies to
revision r0p0. It is fixed in r0p1.

This erratum can be avoided by setting IMP_CPUACTLR_EL1[4] = 1. This
workaround disables early load data return and might have a measurable
performance impact. This erratum affects all configurations where the
BROADCASTMTE pin is HIGH.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1873351/latest

Change-Id: I59cae56c11dc94c5b8f306796631c743b1e00f47
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A510 erratum 2028010

Cortex-A510 erratum 2028010 is a Cat B erratum that applies to
revisions r0p0, r0p1. It is fixed in r0p2.

Software can set IMP_CPUACTLR_EL1[38]

fix(cpus): workaround for Cortex-A510 erratum 2028010

Cortex-A510 erratum 2028010 is a Cat B erratum that applies to
revisions r0p0, r0p1. It is fixed in r0p2.

Software can set IMP_CPUACTLR_EL1[38] = 1. This is not expected to
have a material performance impact in common use cases, but might lead
to some PRF{U}M PLDL1*/PSTL1* instructions not prefetching the cache
line into the L1 data cache.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1873351/latest

Change-Id: I52ac6c17fc4676f4d8c1c95174b298032eec90f1
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A510 erratum 2027318

Cortex-A510 erratum 2027318 is a Cat B erratum that applies to
revisions r0p0, r0p1. It is fixed in r0p2.

This erratum can be avoided by settin

fix(cpus): workaround for Cortex-A510 erratum 2027318

Cortex-A510 erratum 2027318 is a Cat B erratum that applies to
revisions r0p0, r0p1. It is fixed in r0p2.

This erratum can be avoided by setting IMP_CMPXACTLR_EL1[11] = 1. This
workaround has negligible performance impact. This erratum affects
configurations with two cores in a complex.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1873351/latest

Change-Id: I031cbd30145468eb55230199c4f68945fada74ef
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A510 erratum 1975068

Cortex-A510 erratum 1975068 is a Cat B erratum that applies to
revision r0p0. It is fixed in r0p1.

In some systems, software can avoid using No

fix(cpus): workaround for Cortex-A510 erratum 1975068

Cortex-A510 erratum 1975068 is a Cat B erratum that applies to
revision r0p0. It is fixed in r0p1.

In some systems, software can avoid using Non-shareable mappings.
Where that is not possible, software can set IMP_CMPXECTLR_EL1[9:8] =
0b11. This disables early forwarding of L2 hardware prefetches to
subsequent requests, and may incur a small but not negligible
performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1873351/latest

Change-Id: I3ac6cbf43a0bbb798b5e39ee1030376afc1b125a
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A510 erratum 1966377

Cortex-A510 erratum 1966377 is a Cat B erratum that applies to
revision r0p0. It is fixed in r0p1.

This erratum can be avoided by setting IMP_C

fix(cpus): workaround for Cortex-A510 erratum 1966377

Cortex-A510 erratum 1966377 is a Cat B erratum that applies to
revision r0p0. It is fixed in r0p1.

This erratum can be avoided by setting IMP_CPUACTLR2_EL1[29] to 1 to
disable a power optimization feature. This will have no impact on
performance, but will slightly increase power consumption.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1873351/latest

Change-Id: I9b0fb03f7e8b9626a19d3152e4f5047c3bbec1ad
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A510 erratum 1952872

Cortex-A510 erratum 1952872 is a Cat B erratum that applies to
revision r0p0. It is fixed in r0p1.

This erratum can be avoided by setting IMP_C

fix(cpus): workaround for Cortex-A510 erratum 1952872

Cortex-A510 erratum 1952872 is a Cat B erratum that applies to
revision r0p0. It is fixed in r0p1.

This erratum can be avoided by setting IMP_CPUACTLR_EL1[18] = 1. This
workaround may have a small but not negligible performance impact
because the reach of the L1 data TLB is reduced in some cases.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1873351/latest

Change-Id: I1bd0d16cf3071639e37393310b99d7102e9c0490
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A510 erratum 1942494

Cortex-A510 erratum 1942494 is a Cat B erratum that applies to
revision r0p0. It is fixed in r0p1.

This erratum can be avoided by setting IMP_C

fix(cpus): workaround for Cortex-A510 erratum 1942494

Cortex-A510 erratum 1942494 is a Cat B erratum that applies to
revision r0p0. It is fixed in r0p1.

This erratum can be avoided by setting IMP_CPUACTLR_EL1[15] = 1. This
increases the best case L2 hit latency by a cycle, incurring a small
but not negligible performance cost. This erratum affects configurations
where the complex is configured with an L2 cache (configuration
parameter L2_CACHE is TRUE).

SDEN documentation:
https://developer.arm.com/documentation/SDEN1873351/latest

Change-Id: I1956f92457f91815bdb8220c4668cf2f721d1a57
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A510 erratum 1937669

Cortex-A510 erratum 1937669 is a Cat B erratum that applies to
revision r0p0. It is fixed in r0p1.

This erratum can be avoided by setting IMP_C

fix(cpus): workaround for Cortex-A510 erratum 1937669

Cortex-A510 erratum 1937669 is a Cat B erratum that applies to
revision r0p0. It is fixed in r0p1.

This erratum can be avoided by setting IMP_CPUACTLR_EL1[10] = 1. This
upgrades DMB instructions to DSB, potentially incurring a small but
not negligible performance cost.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1873351/latest

Change-Id: Ib8949543a94aaa08560a8b71a84084e3c5d0b30d
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A510 erratum 1910738

Cortex-A510 erratum 1910738 is a Cat B erratum that applies to
revision r0p0. It is fixed in r0p1.

This erratum can be avoided by setting IMP_C

fix(cpus): workaround for Cortex-A510 erratum 1910738

Cortex-A510 erratum 1910738 is a Cat B erratum that applies to
revision r0p0. It is fixed in r0p1.

This erratum can be avoided by setting IMP_CPUECTLR_EL1[19] = 1,
IMP_CPUACTLR_EL1[4] = 1 and IMP_CPUACTLR_EL1[26] = 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1873351/latest

Change-Id: I93ebe8dc7908c52239cfe10d063016a58855f17f
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge changes from topic "xl/cortex_a78c-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A78C erratum 4302974
fix(cpus): workaround for Cortex-A78C erratum 3888019
fix(cpu

Merge changes from topic "xl/cortex_a78c-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A78C erratum 4302974
fix(cpus): workaround for Cortex-A78C erratum 3888019
fix(cpus): update Cortex-A78C WORKAROUND_CVE_2024_5660
fix(cpus): workaround for Cortex-A78C erratum 2779483
fix(cpus): workaround for Cortex-A78C erratum 2478780
fix(cpus): workaround for Cortex-A78C erratum 2395407
fix(cpus): workaround for Cortex-A78C erratum 2376746
fix(cpus): workaround for Cortex-A78C erratum 1951501
fix(cpus): workaround for Cortex-A78C erratum 1941499

show more ...

fix(cpus): workaround for Cortex-A78C erratum 4302974

Cortex-A78C erratum 4302974 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2. It is still open.

This erratum can be avoided by set

fix(cpus): workaround for Cortex-A78C erratum 4302974

Cortex-A78C erratum 4302974 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2. It is still open.

This erratum can be avoided by setting CPUACTLR5_EL1[50] to 1 so that
TLBI instructions correctly honor all ASID bits even when TCR_ELx.AS
is 0.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1707916/latest

Change-Id: I3d938c2d5f5af9257deb8f28256933466f37efc4
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A78C erratum 3888019

Cortex-A78C erratum 3888019 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2. It is still open.

The erratum can be avoided by sett

fix(cpus): workaround for Cortex-A78C erratum 3888019

Cortex-A78C erratum 3888019 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2. It is still open.

The erratum can be avoided by setting CPUACTLR2_EL1[22] to 1, which
disables linking multiple Non-Cacheable or Device GRE loads to the
same read request for a cache line. This might have a significant
performance impact on Non-Cacheable and Device GRE read bandwidth for
streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1707916/latest

Change-Id: I586f030a4fb313ca3b9d299e209d7a5ca90d021a
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge changes from topic "xl/cortex_a77-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A77 erratum 3888015
fix(cpus): update Cortex-A77 applied revision for CVE-2024-5660

Merge changes from topic "xl/cortex_a77-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A77 erratum 3888015
fix(cpus): update Cortex-A77 applied revision for CVE-2024-5660
fix(cpus): workaround for Cortex-A77 erratum 1515815
fix(cpus): workaround for Cortex-A77 erratum 1273521
fix(cpus): workaround for Cortex-A77 erratum 1253791
fix(cpus): workaround for Cortex-A77 erratum 1220737
fix(cpus): workaround for Cortex-A77 erratum 1204882
fix(cpus): workaround for Cortex-A77 erratum 1160841

show more ...

fix(cpus): workaround for Cortex-A78C erratum 2779483

Cortex-A78C erratum 2779483 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2. It is still open.

The erratum can be avoided by sett

fix(cpus): workaround for Cortex-A78C erratum 2779483

Cortex-A78C erratum 2779483 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2. It is still open.

The erratum can be avoided by setting CPUACTLR3_EL1[47]. Setting this
chicken bit might have a small impact on power and a negligible impact
on performance.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1707916/latest

Change-Id: I3f81e16a2dce2a6dfb09b29e9ae6e4cee22ab0ec
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A78C erratum 2478780

Cortex-A78C erratum 2478780 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2. It is still open.

This erratum can be avoided by flu

fix(cpus): workaround for Cortex-A78C erratum 2478780

Cortex-A78C erratum 2478780 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2. It is still open.

This erratum can be avoided by flushing the micro-op cache following a
write to SCR_EL3, HCR_EL2, or SCTLR_ELx. This is implemented through
an implementation-defined sequence of writes to CPUPSELR_EL3,
CPUPOR_EL3, CPUPMR_EL3, and CPUPCR_EL3 at EL3 as soon as possible
after boot, followed by an ISB.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1707916/latest

Change-Id: I2a15a0bd13005518cd856f311577488c1fc31892
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A78C erratum 2395407

Cortex-A78C erratum 2395407 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2. It is still open.

Disable folding of demand requests

fix(cpus): workaround for Cortex-A78C erratum 2395407

Cortex-A78C erratum 2395407 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2. It is still open.

Disable folding of demand requests into older prefetches with L2 miss
requests outstanding by setting CPUACTLR2_EL1[40] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1707916/latest

Change-Id: I3e75fe153f5808dd169e095d386c1f13cd0b02f6
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A78C erratum 2376746

Cortex-A78C erratum 2376746 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2. It is still open.

Set CPUACTLR2_EL1[0] to 1 to force

fix(cpus): workaround for Cortex-A78C erratum 2376746

Cortex-A78C erratum 2376746 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2. It is still open.

Set CPUACTLR2_EL1[0] to 1 to force PLDW and PRFM PST to behave like
PLD and PRFM LD and not cause invalidations to other PE caches. There
might be a small performance degradation for certain workloads that
share data.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1707916/latest

Change-Id: Ibdaef55224d06f3a7332589f4b3c652371c9770c
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A78C erratum 1951501

Cortex-A78C erratum 1951501 is a Cat B erratum that applies to
revision r0p0. It is fixed in r0p1.

This erratum can be avoided by inserting a D

fix(cpus): workaround for Cortex-A78C erratum 1951501

Cortex-A78C erratum 1951501 is a Cat B erratum that applies to
revision r0p0. It is fixed in r0p1.

This erratum can be avoided by inserting a DMB ST before acquire
atomic instructions without release semantics. This can be implemented
through execution of a sequence of MSR writes to
implementation-defined registers at EL3 as soon as possible after
boot, followed by an ISB, to program the hardware to automatically
insert the required barrier.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1707916/latest

Change-Id: If5958270d50dcc54d1d0a168c4b9f2dc3784f3b2
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A78C erratum 1941499

Cortex-A78C erratum 1941499 is a Cat B erratum that applies to
revision r0p0. It is fixed in r0p1.

This erratum can be avoided by setting CPUEC

fix(cpus): workaround for Cortex-A78C erratum 1941499

Cortex-A78C erratum 1941499 is a Cat B erratum that applies to
revision r0p0. It is fixed in r0p1.

This erratum can be avoided by setting CPUECTLR_EL1[8] to 1. There is
a small performance cost (less than 0.5%) for setting this bit.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1707916/latest

Change-Id: I0cecc14ec7bdc28eedb1f7524c1795c8cc55632b
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A77 erratum 3888015

Cortex-A77 erratum 3888015 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1. It is still open.

The erratum can be avoided by settin

fix(cpus): workaround for Cortex-A77 erratum 3888015

Cortex-A77 erratum 3888015 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1. It is still open.

The erratum can be avoided by setting CPUACTLR2_EL1[22] to 1, which
disables linking multiple Non-Cacheable or Device GRE loads to the
same cache-line read request and prevents younger loads from reading
stale data at the cost of reduced Non-Cacheable and Device GRE read
bandwidth.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1152370/latest

Change-Id: I0a356e05dff3dce9b9ba8c924556ebdfae391f67
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A77 erratum 1515815

Cortex-A77 erratum 1515815 is a Cat B erratum that applies to
revisions r0p0, r1p0. It is fixed in r1p1.

Set CPUACTLR_EL1[11] to 1 so that the L

fix(cpus): workaround for Cortex-A77 erratum 1515815

Cortex-A77 erratum 1515815 is a Cat B erratum that applies to
revisions r0p0, r1p0. It is fixed in r1p1.

Set CPUACTLR_EL1[11] to 1 so that the L0 Macro-op cache is flushed for
all context synchronization events, ensuring that only a single
instruction is executed before a software step or halt step exception
is taken.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1152370/latest

Change-Id: I1e6faf5a699734f9a5be848807e9c3fa5110d569
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A77 erratum 1273521

Cortex-A77 erratum 1273521 is a Cat B erratum that applies to revision
r0p0. It is fixed in r1p0.

This erratum can be avoided by setting CPUACTL

fix(cpus): workaround for Cortex-A77 erratum 1273521

Cortex-A77 erratum 1273521 is a Cat B erratum that applies to revision
r0p0. It is fixed in r1p0.

This erratum can be avoided by setting CPUACTLR_EL1[13] to 1 to
increase the mispredict-to-fetch latency, which will have some impact
on performance.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1152370/latest

Change-Id: I34677057ba74721a35bdb34488b5a500397b0e88
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A77 erratum 1253791

Cortex-A77 erratum 1253791 is a Cat B erratum that applies to revision
r0p0. It is fixed in r1p0.

This erratum can be avoided by setting CPUACTL

fix(cpus): workaround for Cortex-A77 erratum 1253791

Cortex-A77 erratum 1253791 is a Cat B erratum that applies to revision
r0p0. It is fixed in r1p0.

This erratum can be avoided by setting CPUACTLR3_EL1[10] to 1, which
prevents parallel execution of divide and square root instructions.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1152370/latest

Change-Id: I76895d167a477246ff5bc6c87237fb4f9724c547
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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