Merge changes from topic "hm/handoff" into integration

* changes:
build: make poetry use existing lock file
feat(arm): add fw handoff support for RESET_TO_BL31
feat(tlc): add host tool for sta

Merge changes from topic "hm/handoff" into integration

* changes:
build: make poetry use existing lock file
feat(arm): add fw handoff support for RESET_TO_BL31
feat(tlc): add host tool for static TL generation

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feat(tlc): add host tool for static TL generation

Transfer List Compiler is a command line tool that enables the static
generation of TL's compliant with version 0.9 of the firmware handoff
specific

feat(tlc): add host tool for static TL generation

Transfer List Compiler is a command line tool that enables the static
generation of TL's compliant with version 0.9 of the firmware handoff
specification. The intent of this tool is to support information passing
via the firmware handoff framework to bootloaders that run without
preceding images (i.e. `RESET_TO_BL31`).

It currently allows for TL's to be statically generated from blobs of
data, and modified by removing/adding TE's. Future work will provide
support for TL generation from configuration file.

Change-Id: Iff670842e34c9ad18eac935248ee2aece43dc533
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Co-authored-by: Charlie Bareham <charlie.bareham@arm.com>

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Merge "feat(fgt2): add support for FEAT_FGT2" into integration

Merge "feat(debugv8p9): add support for FEAT_Debugv8p9" into integration

feat(fgt2): add support for FEAT_FGT2

This patch disables trapping to EL3 when the FEAT_FGT2
specific trap registers are accessed by setting the
SCR_EL3.FGTEn2 bit

Signed-off-by: Arvind Ram Prakash

feat(fgt2): add support for FEAT_FGT2

This patch disables trapping to EL3 when the FEAT_FGT2
specific trap registers are accessed by setting the
SCR_EL3.FGTEn2 bit

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I6d2b614affb9067b2bc3d7bf0ae7d169d031592a

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feat(debugv8p9): add support for FEAT_Debugv8p9

This patch enables FEAT_Debugv8p9 and prevents EL1/0 from
trapping to EL3 when accessing MDSELR_EL1 register by
setting the MDCR_EL3.EBWE bit.

Signed

feat(debugv8p9): add support for FEAT_Debugv8p9

This patch enables FEAT_Debugv8p9 and prevents EL1/0 from
trapping to EL3 when accessing MDSELR_EL1 register by
setting the MDCR_EL3.EBWE bit.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I3613af1dd8cb8c0d3c33dc959f170846c0b9695a

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Merge changes from topic "ck/tf-a/target-properties" into integration

* changes:
build(rzg-layout): split combined targets
build(rcar-layout): split combined targets

build(rzg-layout): split combined targets

This is a small change to split up the generation of the RZ/G layout
images into unique targets. This is predominantly for cleanliness
reasons - Make curren

build(rzg-layout): split combined targets

This is a small change to split up the generation of the RZ/G layout
images into unique targets. This is predominantly for cleanliness
reasons - Make current doesn't know about the `.bin` and `.srec`
binaries generated by the `.elf` target.

Change-Id: I81251ac647b85c5eec8f910ddc841a5a32b49e67
Signed-off-by: Chris Kay <chris.kay@arm.com>

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build(rcar-layout): split combined targets

This is a small change to split up the generation of the R-Car layout
images into unique targets. This is predominantly for cleanliness
reasons - Make curr

build(rcar-layout): split combined targets

This is a small change to split up the generation of the R-Car layout
images into unique targets. This is predominantly for cleanliness
reasons - Make current doesn't know about the `.bin` and `.srec`
binaries generated by the `.elf` target.

Change-Id: I624bc0c62e99cead66a6d6e25ff016aecf6b985a
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge "chore(rdv3): rename platform RD-Fremont to RD-V3" into integration

chore(rdv3): rename platform RD-Fremont to RD-V3

Arm has decided to rename RD-Fremont to RD-V3 to align with its
existing product lineup, such as RD-V1, RD-V2, etc. This change
replaces all occurenc

chore(rdv3): rename platform RD-Fremont to RD-V3

Arm has decided to rename RD-Fremont to RD-V3 to align with its
existing product lineup, such as RD-V1, RD-V2, etc. This change
replaces all occurences of "Fremont" with "V3" in file names and
contents.

Change-Id: I302103492f962a7ac74854633ad68701b2a7f420
Signed-off-by: Jerry Wang <Jerry.Wang4@arm.com>

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Merge changes Ida537d4c,Ieda75bba into integration

* changes:
build(encrypt-fw): don't generate `build_msg.c`
build(cert-create): don't generate `build_msg.c`

build(encrypt-fw): don't generate `build_msg.c`

This change avoids generating a build message source file on the shell,
instead using the `__DATE__` and `__TIME__` macros directly.

Change-Id: Ida53

build(encrypt-fw): don't generate `build_msg.c`

This change avoids generating a build message source file on the shell,
instead using the `__DATE__` and `__TIME__` macros directly.

Change-Id: Ida537d4c3e550f2fbbd977472ed6573491d17c23
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge changes from topic "add_s32cc_clk_skeleton" into integration

* changes:
feat(s32g274a): use s32cc clock driver
feat(nxp-drivers): add clock skeleton for s32cc

feat(nxp-drivers): add clock skeleton for s32cc

The S32CC is an umbrella for S32G2, S32G3 and S32R45 SoCs; therefore,
this clock driver will be used for all of these families.

Change-Id: Iede5371b2

feat(nxp-drivers): add clock skeleton for s32cc

The S32CC is an umbrella for S32G2, S32G3 and S32R45 SoCs; therefore,
this clock driver will be used for all of these families.

Change-Id: Iede5371b212b67cf494a033c62fbfdcbe9b1a879
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge "feat(versal2): add support for AMD Versal Gen 2 platform" into integration

Merge changes from topic "nrd3_support" into integration

* changes:
feat(rdfremont): add support for measured boot at BL1 and BL2
feat(arm): mock support for CCA NV ctr
feat(rdfremont): fetch

Merge changes from topic "nrd3_support" into integration

* changes:
feat(rdfremont): add support for measured boot at BL1 and BL2
feat(arm): mock support for CCA NV ctr
feat(rdfremont): fetch attestation key and token from RSE
feat(psa): introduce generic library for CCA attestation
feat(rdfremont): initialize the rse comms driver
feat(rdfremont): helper to initialize rse-comms with AP-RSE MHUv3
fix(rse): include lib-psa to resolve build
feat(neoverse-rd): add MHUv3 channels on third gen multichip platforms
feat(neoverse-rd): add MHUv3 doorbell channels on third gen platforms
feat(rdfremont): initialize GPT on GPC SMMU block
feat(rdfremont): update Root registers page offset for SMMUv3
feat(rdfremont): enable MTE2 if present on the platform
feat(rdfremont): enable SVE for SWD and NS
feat(rdfremont): enable AMU if present on the platform
feat(rdfremont): enable MPAM if present on the platform
feat(rdfremont): add DRAM pas entries in pas table for multichip
feat(rdfremont): add implementation for GPT setup
feat(rdfremont): integrate DTS files for RD-Fremont variants
feat(rdfremont): add support for RD-Fremont-Cfg2
feat(rdfremont): add support for RD-Fremont-Cfg1
feat(rdfremont): add support for RD-Fremont
feat(neoverse-rd): add scope for RD-Fremont variants
feat(neoverse-rd): add multichip pas entries
feat(neoverse-rd): add pas definitions for third gen platforms
feat(neoverse-rd): add DRAM layout for third gen platforms
feat(neoverse-rd): add SRAM layout for third gen platforms
feat(neoverse-rd): add firmware definitions for third gen platforms
feat(neoverse-rd): add RoS definitions for third gen platforms
feat(neoverse-rd): add CSS definitions for third gen platforms

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feat(versal2): add support for AMD Versal Gen 2 platform

New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal NET platform. System starts with AMD PLM

feat(versal2): add support for AMD Versal Gen 2 platform

New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal NET platform. System starts with AMD PLM
firmware which loads TF-A(bl31) to memory, which is already configured, and
jumps to it. PLM also prepare handoff structure for TF-A with information
what components were load and flags which indicate which EL level SW should
be started.

Change-Id: I5065b1b7ec4ee58e77dc4096747758480c84009c
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>

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feat(neoverse-rd): add scope for RD-Fremont variants

As RD-Fremont and its variants would need a dedicated scope for use,
define the scope 'rdfremont' under the subsection within Neoverse-RD
platfor

feat(neoverse-rd): add scope for RD-Fremont variants

As RD-Fremont and its variants would need a dedicated scope for use,
define the scope 'rdfremont' under the subsection within Neoverse-RD
platforms.

Change-Id: I7066824a33edd893e187ec397298b49392ac35da
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>

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Merge "docs(changelog): changelog for v2.11 release" into integration

docs(changelog): changelog for v2.11 release

Generated this change-log using below command:
npm run release -- --skip.commit --skip.tag --release-as 2.11.0

Change-Id: I34c7b342549781057da1b18116500

docs(changelog): changelog for v2.11 release

Generated this change-log using below command:
npm run release -- --skip.commit --skip.tag --release-as 2.11.0

Change-Id: I34c7b342549781057da1b18116500f110bc3f5ad
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Signed-off-by: Juan Pablo Conde <JuanPablo.Conde@arm.com>

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Merge changes from topic "add_s32g274ardb2_support" into integration

* changes:
feat(s32g274a): enable BL31 stage
feat(s32g274a): add S32G274ARDB2 board support
feat(nxp-drivers): add Linflex

Merge changes from topic "add_s32g274ardb2_support" into integration

* changes:
feat(s32g274a): enable BL31 stage
feat(s32g274a): add S32G274ARDB2 board support
feat(nxp-drivers): add Linflex driver

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Merge changes from topic "rss_rse_rename" into integration

* changes:
refactor(changelog): change all occurrences of RSS to RSE
refactor(qemu): change all occurrences of RSS to RSE
refactor(fv

Merge changes from topic "rss_rse_rename" into integration

* changes:
refactor(changelog): change all occurrences of RSS to RSE
refactor(qemu): change all occurrences of RSS to RSE
refactor(fvp): change all occurrences of RSS to RSE
refactor(fiptool): change all occurrences of RSS to RSE
refactor(psa): change all occurrences of RSS to RSE
refactor(fvp): remove leftovers from rss measured boot support
refactor(tc): change all occurrences of RSS to RSE
docs: change all occurrences of RSS to RSE
refactor(measured-boot): change all occurrences of RSS to RSE
refactor(rse): change all occurrences of RSS to RSE
refactor(psa): rename all 'rss' files to 'rse'
refactor(tc): rename all 'rss' files to 'rse'
docs: rename all 'rss' files to 'rse'
refactor(measured-boot): rename all 'rss' files to 'rse'
refactor(rss): rename all 'rss' files to 'rse'

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Merge changes from topic "nrd1_refactor" into integration

* changes:
feat(rdn1edge): remove RD-N1-Edge from deprecated list
feat(sgi575): remove SGI-575 from deprecated list
fix(rdn1edge): upd

Merge changes from topic "nrd1_refactor" into integration

* changes:
feat(rdn1edge): remove RD-N1-Edge from deprecated list
feat(sgi575): remove SGI-575 from deprecated list
fix(rdn1edge): update RD-N1-Edge's changelog title
feat(neoverse-rd): add scope for RD-V1-MC
feat(neoverse-rd): add scope for RD-V1
feat(neoverse-rd): add scope for SGI-575
feat(neoverse-rd): disable SPMD_SPM_AT_SEL2 for A75/V1/N1 platforms
feat(neoverse-rd): enable AMU if supported by the platform
refactor(neoverse-rd): clean-up nrd_plat_arm_def1.h file
refactor(neoverse-rd): remove unused defines from platform_def.h
refactor(neoverse-rd): move defines out of platform_def.h
refactor(neoverse-rd): rename definitions in nrd_ros_fw_def1.h file
refactor(neoverse-rd): rename definitions in nrd_ros_def1.h file
refactor(neoverse-rd): rename definitions in nrd_css_fw_def1.h file
refactor(neoverse-rd): rename definitions in nrd_css_def1.h file
refactor(neoverse-rd): rewrite CSS and RoS device mmap macros
refactor(neoverse-rd): refactor mmap macro for RoS device memory region
refactor(neoverse-rd): refactor mmap macro for CSS device memory region
refactor(neoverse-rd): migrate mmap entry from nrd_plat1.c
refactor(neoverse-rd): rename nrd_plat.c file
refactor(neoverse-rd): refactor nrd_soc_css_def.h file
refactor(neoverse-rd): refactor nrd_soc_platform_def.h file
refactor(neoverse-rd): move away from nrd_base_platform_def.h
refactor(neoverse-rd): remove inclusion of nrd_base_platform_def.h
refactor(neoverse-rd): header files for first generation platforms
refactor(neoverse-rd): refactor scope for Neoverse RD platforms

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feat(s32g274a): add S32G274ARDB2 board support

S32G274ARDB2 is a development board to showcase the capabilities of the
S32G2 SoC. It includes 4 ARM Cortex-A53 cores running at 1.0GHz, 4GBs
of DDR, a

feat(s32g274a): add S32G274ARDB2 board support

S32G274ARDB2 is a development board to showcase the capabilities of the
S32G2 SoC. It includes 4 ARM Cortex-A53 cores running at 1.0GHz, 4GBs
of DDR, accelerators for automotive networking and many other
peripherals.

The added support is minimal and only includes the BL2 stage, with no
MMU enabled. The FIP is preloaded by the BootROM in SRAM, and BL2 copies
BL31 and BL33 from FIP to their designated addresses.

Change-Id: Iedda23302768ab70d63787117c5f6f3c21eb9842
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Dan Nica <dan.nica@nxp.com>
Signed-off-by: Andra-Teodora Ilie <andra.ilie@nxp.com>
Signed-off-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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