Merge changes from topic "hm/handoff-aarch32" into integration

* changes:
refactor(arm): simplify early platform setup functions
feat(bl32): enable r3 usage for boot args
feat(handoff): add li

Merge changes from topic "hm/handoff-aarch32" into integration

* changes:
refactor(arm): simplify early platform setup functions
feat(bl32): enable r3 usage for boot args
feat(handoff): add lib to sp-min sources
feat(handoff): add 32-bit variant of SRAM layout
feat(handoff): add 32-bit variant of ep info
fix(aarch32): avoid using r12 to store boot params
fix(arm): reinit secure and non-secure tls
refactor(handoff): downgrade error messages

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Merge changes from topic "dtpm_poc" into integration

* changes:
feat(docs): update mboot threat model with dTPM
docs(tpm): add design documentation for dTPM
fix(rpi3): expose BL1_RW to BL2 ma

Merge changes from topic "dtpm_poc" into integration

* changes:
feat(docs): update mboot threat model with dTPM
docs(tpm): add design documentation for dTPM
fix(rpi3): expose BL1_RW to BL2 map for mboot
feat(rpi3): add dTPM backed measured boot
feat(tpm): add Infineon SLB9670 GPIO SPI config
feat(tpm): add tpm drivers and framework
feat(io): add generic gpio spi bit-bang driver
feat(rpi3): implement eventlog handoff to BL33
feat(rpi3): implement mboot for rpi3

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feat(tpm): add tpm drivers and framework

Add tpm2 drivers to tf-a with adequate framework
-implement a fifo spi interface that works
with discrete tpm chip.
-implement tpm command layer interfaces

feat(tpm): add tpm drivers and framework

Add tpm2 drivers to tf-a with adequate framework
-implement a fifo spi interface that works
with discrete tpm chip.
-implement tpm command layer interfaces that are used
to initialize, start and make measurements and
close the interface.
-tpm drivers are built using their own make file
to allow for ease in porting across platforms,
and across different interfaces.

Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
Signed-off-by: Abhi Singh <abhi.singh@arm.com>
Change-Id: Ie1a189f45c80f26f4dea16c3bd71b1503709e0ea

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fix(aarch32): avoid using r12 to store boot params

The current implementation uses the `r12` register as temporary storage
for r4. However, `r12` is a call-clobbered register, meaning its
contents a

fix(aarch32): avoid using r12 to store boot params

The current implementation uses the `r12` register as temporary storage
for r4. However, `r12` is a call-clobbered register, meaning its
contents are not preserved across function calls. This becomes
problematic when we later call the `zeromem` function, as any
information stored in `r12` will be lost. To address this issue, we
should avoid using `r12` to store boot parameters.

Change-Id: If94b7fc3a01bc617ceadaaa704d5aa5e5accfd3f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge "chore(dependabot): limit LTS branches to patch updates" into integration

chore(dependabot): limit LTS branches to patch updates

This change adjusts the Dependabot settings for the LTS branches such
that Dependabot does not open pull requests for changes which anything
mo

chore(dependabot): limit LTS branches to patch updates

This change adjusts the Dependabot settings for the LTS branches such
that Dependabot does not open pull requests for changes which anything
more substantial than patch updates (typically security fixes).

Change-Id: Icc203038e8069e723926849a33c3e8784b544053
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge "docs(changelog): remove FEAT_XXXX scopes" into integration

docs(changelog): remove FEAT_XXXX scopes

We have one entry per CPU features but most of the time we just add
CPU feature and its not touched again, so considering to generalize
anything with FEAT_XX

docs(changelog): remove FEAT_XXXX scopes

We have one entry per CPU features but most of the time we just add
CPU feature and its not touched again, so considering to generalize
anything with FEAT_XXXX additions to use `cpufeat` as subsection scope.

Also, some time we don't add a scope for CPU feature this causes problem
while generating release notes as CPU feature additions ends up in wrong
section.

Change-Id: Ibc80f6cdab9ae10ec3af1485640f46771b382da0
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "docs(changelog): add subsection common" into integration

docs(changelog): add subsection common

Introduce subsection common under Arm.

Change-Id: I24177b5ab1636af56aab3c55b21f2ca014546b9c
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

Merge changes I32b0dd2b,I04d88fb6,I9426cf7b,Ia18824a7 into integration

* changes:
docs(changelog): add some architecture features
docs(changelog): create SPD scopes
docs(changelog): update som

Merge changes I32b0dd2b,I04d88fb6,I9426cf7b,Ia18824a7 into integration

* changes:
docs(changelog): add some architecture features
docs(changelog): create SPD scopes
docs(changelog): update some scope for release note
docs(changelog): add subsections for STM32MP25

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docs(changelog): add some architecture features

Add missing scopes for FEAT_SCTLR2, FEAT_D128 and FEAT_THE.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I32b0dd2bdf68a5a56f8b236155a

docs(changelog): add some architecture features

Add missing scopes for FEAT_SCTLR2, FEAT_D128 and FEAT_THE.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I32b0dd2bdf68a5a56f8b236155ad44686d853eca

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docs(changelog): create SPD scopes

Create scopes for Secure Payload dispatchers (OP-TEE, ProvenCore,
Trusty, TSP and Trusted Little Kernel).

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change

docs(changelog): create SPD scopes

Create scopes for Secure Payload dispatchers (OP-TEE, ProvenCore,
Trusty, TSP and Trusted Little Kernel).

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I04d88fb6839d8cc1d87d0962f0a499a5e90c8680

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docs(changelog): update some scope for release note

To ease release note preparation, add some missing scope in the
changelog.yaml file.

Change-Id: I9426cf7b90455a487c4653c3fc9a6a718c13df7b
Signed-

docs(changelog): update some scope for release note

To ease release note preparation, add some missing scope in the
changelog.yaml file.

Change-Id: I9426cf7b90455a487c4653c3fc9a6a718c13df7b
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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docs(changelog): add subsections for STM32MP25

The STM32MP2 family has 3 different types of SoCs (STM32MP25, STM32MP23
and STM32MP21). For the moment only STM32MP25 is partly supported in
TF-A. Add

docs(changelog): add subsections for STM32MP25

The STM32MP2 family has 3 different types of SoCs (STM32MP25, STM32MP23
and STM32MP21). For the moment only STM32MP25 is partly supported in
TF-A. Add a dedicated subsections for STM32MP25. The other ones will be
added later. The same is done for FDTS scope.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: Ia18824a7b649bcd1ffa631e3aa0ecb3fd0b2d038

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Merge "refactor(delay-timer): add timer callback functions" into integration

refactor(delay-timer): add timer callback functions

In order to avoid separate platform definitions when not using the
default timer functions, it is better to move these functions out of the
header

refactor(delay-timer): add timer callback functions

In order to avoid separate platform definitions when not using the
default timer functions, it is better to move these functions out of the
header file and into the source files, so that they can be built if
needed.

Move timer functions from delay_timer.h into generic_delay_timer.c. Add
them as callback functions which are then called in delay_timer.c.

Change-Id: I96a1eac8948b1a7b1e481899b67a083db4c9b97d
Signed-off-by: Abhi Singh <abhi.singh@arm.com>

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Merge changes from topic "rd1ae-upstream" into integration

* changes:
docs(rd1ae): add RD-1 AE documentation
feat(rd1ae): enabling Trusted Board Boot(TBB) for RD-1 AE
feat(rd1ae): introduce BL

Merge changes from topic "rd1ae-upstream" into integration

* changes:
docs(rd1ae): add RD-1 AE documentation
feat(rd1ae): enabling Trusted Board Boot(TBB) for RD-1 AE
feat(rd1ae): introduce BL31 for RD-1 AE platform
feat(rd1ae): add device tree files
feat(rd1ae): introduce Arm RD-1 AE platform
build(bl2): enable check for bl2 base overflow assert
feat(arm): add support for loading CONFIG from BL2

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feat(rd1ae): introduce Arm RD-1 AE platform

Create a new platform for the RD-1 AE automotive FVP.
This platform contains:
* Neoverse-V3AE, Arm9.2-A application processor
* A GICv4-compatible GIC-7

feat(rd1ae): introduce Arm RD-1 AE platform

Create a new platform for the RD-1 AE automotive FVP.
This platform contains:
* Neoverse-V3AE, Arm9.2-A application processor
* A GICv4-compatible GIC-720AE
* 128 MB of SRAM, of which 1 MB is reserved for TF-A

and BL2 runs at ELmax (EL3).

Additionally, this commit updates the maintainers.rst file and
the changelog.yaml to add scope for RD-1 AE variants.

Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
Signed-off-by: Divin Raj <divin.raj@arm.com>
Signed-off-by: Rahul Singh <rahul.singh@arm.com>
Change-Id: I9ae64b3f05a52653ebd1d334b15b7f21821264e2

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Merge changes from topic "mb/misc-fixes" into integration

* changes:
docs: fix typos in cot binding
fix(drtm): return proper values for DRTM get and set error SMCs
fix(tools): update the fipto

Merge changes from topic "mb/misc-fixes" into integration

* changes:
docs: fix typos in cot binding
fix(drtm): return proper values for DRTM get and set error SMCs
fix(tools): update the fiptool and certtool to fix POSIX build

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fix(tools): update the fiptool and certtool to fix POSIX build

This patch fixes below issue raised:

https://github.com/TrustedFirmware-A/trusted-firmware-a/issues/8
https://github.com/TrustedFirmwa

fix(tools): update the fiptool and certtool to fix POSIX build

This patch fixes below issue raised:

https://github.com/TrustedFirmware-A/trusted-firmware-a/issues/8
https://github.com/TrustedFirmware-A/trusted-firmware-a/issues/9
https://github.com/TrustedFirmware-A/trusted-firmware-a/issues/10

Change-Id: I521bf7410535ffe49198789ba183cc401b3b88a0
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge changes from topic "mb/cot-fixes" into integration

* changes:
fix(cot-dt2c): fix various breakages
fix(cot-dt2c): use processed Device Tree source file as input

fix(cot-dt2c): use processed Device Tree source file as input

Update the test files to eliminate the use of preprocessor macros,
as the tool now requires processed output. The documentation has
also

fix(cot-dt2c): use processed Device Tree source file as input

Update the test files to eliminate the use of preprocessor macros,
as the tool now requires processed output. The documentation has
also been revised accordingly.

Additionally, remove the Device Tree Source test files that were
added to test the #ifdef conditions.

Change-Id: I13a682db20e5e44170fc25a2e2dbedd45b9c7321
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge changes from topic "mp/simd_ctxt_mgmt" into integration

* changes:
feat(fvp): allow SIMD context to be put in TZC DRAM
docs(simd): introduce CTX_INCLUDE_SVE_REGS build flag
feat(fvp): ad

Merge changes from topic "mp/simd_ctxt_mgmt" into integration

* changes:
feat(fvp): allow SIMD context to be put in TZC DRAM
docs(simd): introduce CTX_INCLUDE_SVE_REGS build flag
feat(fvp): add Cactus partition manifest for EL3 SPMC
chore(simd): remove unused macros and utilities for FP
feat(el3-spmc): support simd context management upon world switch
feat(trusty): switch to simd_ctx_save/restore apis
feat(pncd): switch to simd_ctx_save/restore apis
feat(spm-mm): switch to simd_ctx_save/restore APIs
feat(simd): add rules to rationalize simd ctxt mgmt
feat(simd): introduce simd context helper APIs
feat(simd): add routines to save, restore sve state
feat(simd): add sve state to simd ctxt struct
feat(simd): add data struct for simd ctxt management

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feat(simd): add data struct for simd ctxt management

From a context management perspective, we refer to SVE and FP state
as SIMD. SVE can be considered as a superset of FP/NEON functionality
and the

feat(simd): add data struct for simd ctxt management

From a context management perspective, we refer to SVE and FP state
as SIMD. SVE can be considered as a superset of FP/NEON functionality
and there is a architectural dependency between the two due to the fact
that FP registers occupy the bottom 128 bits of SVE Z vector registers.

This patch introduces a new data structure to hold the FP state of a CPU
as needed for context management operations during world switch events.
It will evolve in next patches to capture the SVE state as well.

Having this unified data structure is necessary for us to implement
SIMD context management while catering to various build configurations.

Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: If2a9a7526883780df49bbd3dade2f09f7c3d95ae

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