docs(changelog): changelog for v2.7 release

Change-Id: I573e5eb3c7fad097892292c8a967dc02d72d12e6
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

Merge changes from topic "mb/drtm-work-phase-1" into integration

* changes:
build(changelog): add new scope for Arm SMMU driver
feat(smmu): add SMMU abort transaction function
docs(build): add

Merge changes from topic "mb/drtm-work-phase-1" into integration

* changes:
build(changelog): add new scope for Arm SMMU driver
feat(smmu): add SMMU abort transaction function
docs(build): add build option for DRTM support
build(drtm): add DRTM support build option

show more ...

Merge "build(changelog): add new scope for the threat model" into integration

build(changelog): add new scope for Arm SMMU driver

Added new scope for Arm SMMU driver.

Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Change-Id: I62f5ed36657a071d125cdddacbff9fb23d2bc

build(changelog): add new scope for Arm SMMU driver

Added new scope for Arm SMMU driver.

Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Change-Id: I62f5ed36657a071d125cdddacbff9fb23d2bc8e0

show more ...

build(changelog): add new scope for the threat model

Change-Id: I884f31f7f4b5515c420839ff37d401faa69f5fff
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Merge "build(changelog): add new scope for TI platform" into integration

Merge changes from topics "ls1088a", "ls1088a-prepare" into integration

* changes:
docs(layerscape): add ls1088a soc and board support
feat(ls1088aqds): add ls1088aqds board support
feat(ls108

Merge changes from topics "ls1088a", "ls1088a-prepare" into integration

* changes:
docs(layerscape): add ls1088a soc and board support
feat(ls1088aqds): add ls1088aqds board support
feat(ls1088ardb): add ls1088ardb board support
feat(ls1088a): add new SoC platform ls1088a
build(changelog): add new scopes for ls1088a
feat(bl2): add support to separate no-loadable sections
refactor(layerscape): refine comparison of inerconnection
feat(layerscape): add soc helper macro definition for chassis 3
feat(nxp-gic): add some macros definition for gicv3
feat(layerscape): add CHASSIS 3 support for tbbr
feat(layerscape): define more chassis 3 hardware address
feat(nxp-crypto): add chassis 3 support
feat(nxp-dcfg): add Chassis 3 support
feat(lx2): enable DDR erratas for lx2 platforms
feat(layerscape): print DDR errata information
feat(nxp-ddr): add workaround for errata A050958
feat(layerscape): add new soc errata a010539 support
feat(layerscape): add new soc errata a009660 support
feat(nxp-ddr): add rawcard 1F support
fix(layerscape): fix build issue of mmap_add_ddr_region_dynamically
fix(nxp-tools): fix create_pbl print log
build(changelog): add new scopes for NXP driver

show more ...

build(changelog): add new scopes for ls1088a

Add new scopes for ls1088a SoC, RDB and QDS boards.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I7c0018ecee3c590253cf258851a28c4dd7f9c1a1

build(changelog): add new scopes for NXP driver

Add new scope for NXP DDR drivers and GIC drivers.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I8ff4d203c474593fe2cff846e0040fc8651b20b6

build(changelog): add new scope for TI platform

Add new scope for TI and K3 platforms.

Change-Id: I3b666c73e3ee8bcf73fcd155b7a372f44b56b033
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>

Merge changes I75b3e3bf,I4cf9f1d9,I50d2ae74,Idbe62410,I84bbd06e, ... into integration

* changes:
fix(intel): null pointer handling for resp_len
fix(intel): define macros to handle buffer entries

Merge changes I75b3e3bf,I4cf9f1d9,I50d2ae74,Idbe62410,I84bbd06e, ... into integration

* changes:
fix(intel): null pointer handling for resp_len
fix(intel): define macros to handle buffer entries
fix(intel): change SMC return arguments for INTEL_SIP_SMC_MBOX_SEND_CMD
fix(intel): always set doorbell to SDM after sending command
fix(intel): fix bit masking issue in intel_secure_reg_update
fix(intel): fix ddr address range checker
build(changelog): add new scope for Intel platform

show more ...

Merge changes from topic "bug-fix" into integration

* changes:
fix(nxp-crypto): refine code to avoid hang issue for some of toolchain
build(changelog): add new scope for nxp crypto
fix(lx2): d

Merge changes from topic "bug-fix" into integration

* changes:
fix(nxp-crypto): refine code to avoid hang issue for some of toolchain
build(changelog): add new scope for nxp crypto
fix(lx2): drop erratum A-009810

show more ...

build(changelog): add new scope for Intel platform

Add new scope for Intel platform.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I1fa7f5e0e5567825615dd0275b204b82fe8c2337

build(changelog): add new scope for nxp crypto

Add new scope for NXP Crypto CAAM drivers.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I4beb96d1dc655281cb2fc99b8b0b998f35499dba

Merge changes from topic "ls1046a" into integration

* changes:
docs(layerscape): add ls1046a soc and board support
feat(ls1046aqds): add board ls1046aqds support
feat(ls1046afrwy): add ls1046a

Merge changes from topic "ls1046a" into integration

* changes:
docs(layerscape): add ls1046a soc and board support
feat(ls1046aqds): add board ls1046aqds support
feat(ls1046afrwy): add ls1046afrwy board support
feat(ls1046ardb): add ls1046ardb board support
feat(ls1046a): add new SoC platform ls1046a
fix(nxp-tools): fix tool location path for byte_swape
fix(nxp-qspi): fix include path for QSPI driver
build(changelog): add new scopes for NXP layerscape platforms

show more ...

build(changelog): add new scopes for NXP layerscape platforms

1. Add scopes for ls1046a and related boards: ls1046ardb,
ls1046aqds, ls1046afwry.
2. Add new scope for NXP QSPI driver.
3. Add new scop

build(changelog): add new scopes for NXP layerscape platforms

1. Add scopes for ls1046a and related boards: ls1046ardb,
ls1046aqds, ls1046afwry.
2. Add new scope for NXP QSPI driver.
3. Add new scope for NXP tools.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I68ef7dd25628b393dbfbb8dbf59d5185945ea61c

show more ...

Merge "feat(spe): add support for FEAT_SPEv1p2" into integration

feat(spe): add support for FEAT_SPEv1p2

Allow access to PMSNEVFR_EL1 register at NS-EL1 or NS-EL2 when
FEAT_SPEv1p2 is implemented.

Change-Id: I44b1de93526dbe9c11fd061d876371a6c0e6fa9c
Signed-off-b

feat(spe): add support for FEAT_SPEv1p2

Allow access to PMSNEVFR_EL1 register at NS-EL1 or NS-EL2 when
FEAT_SPEv1p2 is implemented.

Change-Id: I44b1de93526dbe9c11fd061d876371a6c0e6fa9c
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

show more ...

Merge changes from topic "msm8916" into integration

* changes:
feat(msm8916): allow booting secondary CPU cores
feat(msm8916): setup hardware for non-secure world
feat(gic): allow overriding G

Merge changes from topic "msm8916" into integration

* changes:
feat(msm8916): allow booting secondary CPU cores
feat(msm8916): setup hardware for non-secure world
feat(gic): allow overriding GICD_PIDR2_GICV2 address
feat(msm8916): initial platform port
docs(msm8916): new port for Qualcomm Snapdragon 410

show more ...

docs(msm8916): new port for Qualcomm Snapdragon 410

The Qualcomm Snapdragon 410 is Qualcomm's first 64-bit SoC, released
in 2014 with four ARM Cortex-A53 cores. There are differents variants
(MSM891

docs(msm8916): new port for Qualcomm Snapdragon 410

The Qualcomm Snapdragon 410 is Qualcomm's first 64-bit SoC, released
in 2014 with four ARM Cortex-A53 cores. There are differents variants
(MSM8916, APQ8016(E), ...) that are all very similar. A popular device
based on APQ8016E is the DragonBoard 410c single-board computer,
but the SoC is also used in various mid-range smartphones/tablets.

This commit adds documentation for a minimal, community-maintained port
of TF-A/BL31 for MSM8916. The actual platform port is added in the
following four separate small commits to simplify the review process.
The code is primarily based on the information from the public
Snapdragon 410E Technical Reference Manual [1], combined with a lot of
trial and error to actually make it work.

Note that this port is a pure community effort without any
commercial interests and is not related to Qualcomm in any way.
The main motivation for this port is to have a minimal, updatable
firmware since this old chip does not receive many updates anymore from
Qualcomm. It works quite well for many use cases so I am willing to
maintain it as a "code owner". I have also added Nikita Travkin as
second code owner to help with reviews.

The main limitation so far is the lack of memory protection for TF-A.
This is similar to the ports for the Raspberry Pi but in this case not
a lack of hardware support but rather a lack of documentation. However,
this does not limit the usefulness of the port when used as a minimal
PSCI implementation.

[1]: https://developer.qualcomm.com/download/sd410/snapdragon-410e-technical-reference-manual.pdf

Change-Id: I676adf86061638cfc2f3ae8615470d145e84f172
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

show more ...

Merge "docs(commit-style): change blessed scope of FF-A" into integration

docs(commit-style): change blessed scope of FF-A

Also split SPM MM into it's own scope.

Change-Id: I9cfb1ddec7419ad0d7b539f65e7322bbd44a3913
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

Merge "docs(changelog): add some missing ST drivers" into integration

docs(changelog): add some missing ST drivers

Some of the ST drivers were not listed, and had no scopes. Add BSEC,
Crypto, DDR, I2C, FMC, GPIO, Regulator, Reset, SPI and Watchdog.

Signed-off-by: Yan

docs(changelog): add some missing ST drivers

Some of the ST drivers were not listed, and had no scopes. Add BSEC,
Crypto, DDR, I2C, FMC, GPIO, Regulator, Reset, SPI and Watchdog.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I4441f160f778d4bf7686e24e7d2d3c8330891327

show more ...

Merge changes from topic "fwu-on-stm32mp1" into integration

* changes:
feat(stm32mp1): add support for building the FWU feature
feat(stm32mp1): add logic to pass the boot index to the Update Age

Merge changes from topic "fwu-on-stm32mp1" into integration

* changes:
feat(stm32mp1): add support for building the FWU feature
feat(stm32mp1): add logic to pass the boot index to the Update Agent
feat(stm32mp1): add support for reading the metadata partition
feat(stm32mp1): add logic to select the images to be booted
feat(stm32mp1): add GUID's for identifying firmware images to be booted
feat(stm32mp1): add GUID values for updatable images
feat(fwu): add platform hook for getting the boot index
feat(fwu): simplify the assert to check for fwu init
feat(fwu): add a function to pass metadata structure to platforms
feat(partition): add a function to identify a partition by GUID
feat(partition): copy the partition GUID into the partition structure
feat(partition): make provision to store partition GUID value
feat(partition): cleanup partition and gpt headers
feat(fwu): add basic definitions for GUID handling
feat(fwu): pass a const metadata structure to platform routines
build(changelog): add a valid scope for partition code

show more ...