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a97e1f97 |
| 08-May-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "early_console" into integration
* changes: feat(stm32mp2): use early traces feat(st-bsec): use early traces refactor(st): replace STM32MP_EARLY_CONSOLE with EARLY_CON
Merge changes from topic "early_console" into integration
* changes: feat(stm32mp2): use early traces feat(st-bsec): use early traces refactor(st): replace STM32MP_EARLY_CONSOLE with EARLY_CONSOLE feat(console): introduce EARLY_CONSOLE feat(bl32): create an sp_min_setup function
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| #
a1255c75 |
| 18-Jan-2024 |
Yann Gautier <yann.gautier@st.com> |
feat(bl32): create an sp_min_setup function
This new C function will call sp_min_early_platform_setup2() and sp_min_plat_arch_setup(). At this step the C environment is already enabled, and it allow
feat(bl32): create an sp_min_setup function
This new C function will call sp_min_early_platform_setup2() and sp_min_plat_arch_setup(). At this step the C environment is already enabled, and it allows adding function like the one for early console for which r9-r12 registers could be clobbered.
Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I4cbf2f6acea769d595ff40b2e2b4ca5d29672878
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| #
8742f857 |
| 26-Apr-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "rk3288" into integration
* changes: rockchip: document platform rockchip: add support for rk3288 rockchip: add common aarch32 support rockchip: rk3328: drop double
Merge changes from topic "rk3288" into integration
* changes: rockchip: document platform rockchip: add support for rk3288 rockchip: add common aarch32 support rockchip: rk3328: drop double declaration of entry_point storage rockchip: Allow socs with undefined wfe check bits rockchip: move pmusram assembler code to a aarch64 subdir sp_min: allow inclusion of a platform-specific linker script sp_min: make sp_min_warm_entrypoint public drivers: ti: uart: add a aarch32 variant
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| #
d4c98a1b |
| 02-Mar-2019 |
Heiko Stuebner <heiko@sntech.de> |
sp_min: make sp_min_warm_entrypoint public
Similar to bl31_warm_entrypoint, sp_min-based platforms may need that for special resume handling.
Therefore move it from the private header to the sp_min
sp_min: make sp_min_warm_entrypoint public
Similar to bl31_warm_entrypoint, sp_min-based platforms may need that for special resume handling.
Therefore move it from the private header to the sp_min platform header.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I40d9eb3ff77cff88d47c1ff51d53d9b2512cbd3e
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| #
9d068f66 |
| 08-Nov-2018 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1673 from antonio-nino-diaz-arm/an/headers
Standardise header guards across codebase
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c3cf06f1 |
| 08-Nov-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Standardise header guards across codebase
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards.
The style that this proje
Standardise header guards across codebase
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards.
The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H.
The exceptions are files that are imported from other projects:
- CryptoCell driver - dt-bindings folders - zlib headers
Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| #
e8082422 |
| 17-Aug-2017 |
danh-arm <dan.handley@arm.com> |
Merge pull request #977 from etienne-lms/sp-min-fiq
bl32: add secure interrupt handling in AArch32 sp_min
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| #
71816096 |
| 09-Aug-2017 |
Etienne Carriere <etienne.carriere@st.com> |
bl32: add secure interrupt handling in AArch32 sp_min
Add support for a minimal secure interrupt service in sp_min for the AArch32 implementation. Hard code that only FIQs are handled.
Introduce bo
bl32: add secure interrupt handling in AArch32 sp_min
Add support for a minimal secure interrupt service in sp_min for the AArch32 implementation. Hard code that only FIQs are handled.
Introduce bolean build directive SP_MIN_WITH_SECURE_FIQ to enable FIQ handling from SP_MIN.
Configure SCR[FIQ] and SCR[FW] from generic code for both cold and warm boots to handle FIQ in secure state from monitor.
Since SP_MIN architecture, FIQ are always trapped when system executes in non secure state. Hence discard relay of the secure/non-secure state in the FIQ handler.
Change-Id: I1f7d1dc7b21f6f90011b7f3fcd921e455592f5e7 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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| #
f132b4a0 |
| 04-May-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #925 from dp-arm/dp/spdx
Use SPDX license identifiers
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| #
82cb2c1a |
| 03-May-2017 |
dp-arm <dimitris.papastamos@arm.com> |
Use SPDX license identifiers
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file.
NOTE: Files that have been imported by
Use SPDX license identifiers
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file.
NOTE: Files that have been imported by FreeBSD have not been modified.
[0]: https://spdx.org/
Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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937108a0 |
| 18-Aug-2016 |
danh-arm <dan.handley@arm.com> |
Merge pull request #678 from soby-mathew/sm/PSCI_AArch32
Introduce AArch32 support for PSCI library
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| #
c11ba852 |
| 05-May-2016 |
Soby Mathew <soby.mathew@arm.com> |
AArch32: add a minimal secure payload (SP_MIN)
This patch adds a minimal AArch32 secure payload SP_MIN. It relies on PSCI library to initialize the normal world context. It runs in Monitor mode and
AArch32: add a minimal secure payload (SP_MIN)
This patch adds a minimal AArch32 secure payload SP_MIN. It relies on PSCI library to initialize the normal world context. It runs in Monitor mode and uses the runtime service framework to handle SMCs. It is added as a BL32 component in the Trusted Firmware source tree.
Change-Id: Icc04fa6b242025a769c1f6c7022fde19459c43e9
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