Merge changes from topic "map-summary" into integration

* changes:
feat(memmap): add summary command to memory map script
refactor(memmap)!: change behavioural flags to commands
refactor(memma

Merge changes from topic "map-summary" into integration

* changes:
feat(memmap): add summary command to memory map script
refactor(memmap)!: change behavioural flags to commands
refactor(memmap): fix typing-related issues
refactor(memmap): create common image parser interface
refactor(memmap): represent image symbols with key-value map
refactor(memmap): factor memory regions into their own structure
refactor(memmap): apply additional type hints
refactor(memmap): check ELF object type rather than flag
refactor(memmap): remove unused functionality
fix(memmap): ensure terminal width is respected
style(memmap): format with Ruff

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Merge changes I2af839ae,Ifd0c7b4e,I56763cb4,I93aec580,Icbd43503, ... into integration

* changes:
docs(fvp): add GICv5 build instructions and limitations
feat(fvp): add GICv5 support
feat(gicv5

Merge changes I2af839ae,Ifd0c7b4e,I56763cb4,I93aec580,Icbd43503, ... into integration

* changes:
docs(fvp): add GICv5 build instructions and limitations
feat(fvp): add GICv5 support
feat(gicv5): probe components
feat(gicv5): initialise the IWB
feat(gicv5): initialise the IRS
feat(gicv5): assign interrupt sources to appropriate security states
feat(gicv5): add a barebones GICv5 driver
feat(gicv5): add support for building with gicv5

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feat(gicv5): add support for building with gicv5

The Generic Interrupt Controller v5 (GICv5) is the next generation of
Arm interrupt controllers. It is a clean slate design and has native
support fo

feat(gicv5): add support for building with gicv5

The Generic Interrupt Controller v5 (GICv5) is the next generation of
Arm interrupt controllers. It is a clean slate design and has native
support for the latest Armv9 features. As such it is entirely backwards
incompatible with GICv3/v4.

This patch adds the necessary boilerplate to select a build with GICv5.
The GIC has always had two parts. BL31 deals directly with the CPU
interface while platform code is responsible for managing the IRI. In v5
this split is formalised and the CPU interface, FEAT_GCIE, may be
implemented on its own. So reflect this split in our code with
ENABLE_FEAT_GCIE which only affects BL31 and the GICv5 IRI lies in the
generic GIC driver.

No actual functionality yet.

Change-Id: I97a0c3ba708877c213e50e7ef148e3412aa2af90
Co-developed-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(memmap)!: change behavioural flags to commands

This change factors out the following memory map tool flags into
independent commands:

- `--footprint` (becomes `memory footprint`)
- `--tree

refactor(memmap)!: change behavioural flags to commands

This change factors out the following memory map tool flags into
independent commands:

- `--footprint` (becomes `memory footprint`)
- `--tree` (becomes `memory tree`)
- `--symbol` (becomes `memory symbol`)

So, for example, where previously you would generate the memory
footprint of a build with:

memory --tree

You would now instead use:

memory footprint

Any flags specific to a command (e.g. `--depth` for `tree`) must be
specified after the command, e.g.

memory tree --depth 1

... instead of:

memory --depth 1 tree

BREAKING-CHANGE: The image memory map visualization tool now uses
commands, rather than arguments, to determine the behaviour of the
script. See the commit message for further details.

Change-Id: I11d54d1f6276b8447bdfb8496544ab80399459ac
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge "fix(build): remove SUPPORT_STACK_MEMTAG" into integration

fix(build): remove SUPPORT_STACK_MEMTAG

This flag enables the memtag sanitizer in clang. However, for this to
work, other generic and platform-specific logic is required that was
never implemented.

fix(build): remove SUPPORT_STACK_MEMTAG

This flag enables the memtag sanitizer in clang. However, for this to
work, other generic and platform-specific logic is required that was
never implemented. So in effect, the feature is half-baked and at best a
simple test (of which we have plenty in tftf) or a NOP at worst.

So remove the option to simplify code a little.

Change-Id: Iab4150871c89545d813c5ae14be67bf6459d051a
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "build(poetry): wrap docs build in poetry" into integration

build(poetry): wrap docs build in poetry

Simplify building documentation by wrapping the Sphinx command inside
a Poetry environment. Previously, the developer had to manually
activate Poetry and in

build(poetry): wrap docs build in poetry

Simplify building documentation by wrapping the Sphinx command inside
a Poetry environment. Previously, the developer had to manually
activate Poetry and install the docs group. This change makes the
process consistent with other build targets and reduces user error.
Falls back gracefully if Poetry is not installed.

Change-Id: I1dfea58314253773bec5e2c70d27e2216e3143d9
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge "docs(changelog): changelog for v2.13 release" into integration

docs(changelog): changelog for v2.13 release

Generated this change-log using below command:
npm run release -- --skip.commit --skip.tag --release-as 2.13.0

Change-Id: Ibb0623f04c641b65a03deaffd50a5

docs(changelog): changelog for v2.13 release

Generated this change-log using below command:
npm run release -- --skip.commit --skip.tag --release-as 2.13.0

Change-Id: Ibb0623f04c641b65a03deaffd50a5a8b65637419
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes from topic "fix_pmuv3p9_test" into integration

* changes:
fix(smccc): properly set RAS feature bit
fix(trng): allow FEAT_RNG_TRAP in dynamic fashion
feat(smccc): add FEAT_TWED to

Merge changes from topic "fix_pmuv3p9_test" into integration

* changes:
fix(smccc): properly set RAS feature bit
fix(trng): allow FEAT_RNG_TRAP in dynamic fashion
feat(smccc): add FEAT_TWED to ARCH_FEATURE_AVAILABILITY
feat(cpufeat): add support for PMUv3p9

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Merge "feat(cpufeat): add support for FEAT_PAUTH_LR" into integration

feat(cpufeat): add support for FEAT_PAUTH_LR

This patch enables FEAT_PAUTH_LR at EL3 on systems that support it when
the new ENABLE_FEAT_PAUTH_LR flag is set.

Currently, PAUTH_LR is only supported

feat(cpufeat): add support for FEAT_PAUTH_LR

This patch enables FEAT_PAUTH_LR at EL3 on systems that support it when
the new ENABLE_FEAT_PAUTH_LR flag is set.

Currently, PAUTH_LR is only supported by arm clang compiler and not GCC.

Change-Id: I7db1e34b661ed95cad75850b62878ac5d98466ea
Signed-off-by: John Powell <john.powell@arm.com>

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Merge changes I86959e67,I0b0d1d36,I5b5267f4,I056c8710,I3474aa97 into integration

* changes:
chore: fix preprocessor checks
refactor: convert arm platforms to use the generic GIC driver
refacto

Merge changes I86959e67,I0b0d1d36,I5b5267f4,I056c8710,I3474aa97 into integration

* changes:
chore: fix preprocessor checks
refactor: convert arm platforms to use the generic GIC driver
refactor(gic): promote most of the GIC driver to common code
refactor: make arm_gicv2.c and arm_gicv3.c common
refactor(fvp): use more arm generic code for gicv3

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refactor(gic): promote most of the GIC driver to common code

More often than not, Arm based systems include some revision of a GIC.
There are two ways of adding support for them in platform code - c

refactor(gic): promote most of the GIC driver to common code

More often than not, Arm based systems include some revision of a GIC.
There are two ways of adding support for them in platform code - calling
the top-level helpers from plat/arm/common/arm_gicvX.c or by using the
driver directly. Both of these methods allow for a high degree of
customisation - most functions are defined to be weak and there are no
calls to any of them in generic code.

As it turns out, requirements around those GICs are largely the same.
Platforms that use arm_gicvX.c use the helpers identically among each
other. Platforms that use the driver directly tend to end up with calls
that look a lot like the arm_gicvX.c helpers and the weakness of the
functions are never exercised.

All of this results in a lot of code duplication to do what is
essentially the same thing. Even though it's not a lot of code, when
multiplied among many platforms it becomes significant and makes
refactoring it quite difficult. It's also bug prone since the steps are
a little convoluted and things are likely to work even with subtle
errors (see 50009f61177421118f42d6a000611ba0e613d54b).

So promote as much of the GIC to be called from common code. Do the
setup in bl31_main() and have every PSCI method do the state management
directly instead of delegating it to the platform hooks. We can base
this implementation on arm_gicvX.c since they already offer logical
names and have worked quite well so far with minimal changes.

The main benefit of doing this is reduced code duplication. If we assume
that, outside of some platform setup, GIC management is identical, then
a platform can add support by telling the build system, regardless of
GIC revision. The other benefit is performance - BL31 and PSCI already
know the core_pos and they can pass it as an argument instead of having
to call plat_my_core_pos(). Now, the only platform specific GIC actions
necessary are the saving and restoring of context on entering and
exiting a power domain. The PSCI library does not keep track of this so
it is unable perform it itself. The routines themselves are also
provided.

For compatibility all of this is hidden behind a build flag. Platforms
are encouraged to adopt this driver, but it would not be practical to
convert and validate every GIC based platform.

This patch renames the functions in question to follow the
gic_<function>() convention. This allows the names to be version
agnostic.

Finally, drop the weak definitions - they are unused, likely to remain
so, and can be added back if the need arises.

Change-Id: I5b5267f4b72f633fb1096400ec8e4b208694135f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes Id942c20c,Idd286bea,I8917a26e,Iec8c3477,If3c25dcd, ... into integration

* changes:
feat(cpufeat): enable FEAT_PAuth to FEAT_STATE_CHECKED
perf(cpufeat): centralise PAuth key saving

Merge changes Id942c20c,Idd286bea,I8917a26e,Iec8c3477,If3c25dcd, ... into integration

* changes:
feat(cpufeat): enable FEAT_PAuth to FEAT_STATE_CHECKED
perf(cpufeat): centralise PAuth key saving
refactor(cpufeat): convert FEAT_PAuth setup to C
refactor(cpufeat): prepare FEAT_PAuth for FEATURE_DETECTION
chore(cpufeat): remove PAuth presence checks
feat(cpufeat): enable FEAT_BTI to FEAT_STATE_CHECKED

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feat(cpufeat): enable FEAT_PAuth to FEAT_STATE_CHECKED

FEAT_PAuth is the second to last feature to be a boolean choice - it's
either unconditionally compiled in and must be present in hardware or
it

feat(cpufeat): enable FEAT_PAuth to FEAT_STATE_CHECKED

FEAT_PAuth is the second to last feature to be a boolean choice - it's
either unconditionally compiled in and must be present in hardware or
it's not compiled in. FEAT_PAuth is architected to be backwards
compatible - a subset of the branch guarding instructions (pacia/autia)
execute as NOPs when PAuth is not present. That subset is used with
`-mbranch-protection=standard` and -march pre-8.3. This patch adds the
necessary logic to also check accesses of the non-backward compatible
registers and allow a fully checked implementation.

Note that a checked support requires -march to be pre 8.3, as otherwise
the compiler will include branch protection instructions that are not
NOPs without PAuth (eg retaa) which cannot be checked.

Change-Id: Id942c20cae9d15d25b3d72b8161333642574ddaa
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(build): update clang target for aarch64" into integration

Merge changes from topic "sm/rpkm" into integration

* changes:
docs(rmmd): document the EL3-RMM IDE KM Interface
feat(trp): test el3-rmm ide km interface
feat(rmmd): el3-rmm ide key management

Merge changes from topic "sm/rpkm" into integration

* changes:
docs(rmmd): document the EL3-RMM IDE KM Interface
feat(trp): test el3-rmm ide km interface
feat(rmmd): el3-rmm ide key management interface

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feat(rmmd): el3-rmm ide key management interface

Patch introduces the EL3-RMM SMC Interface for Root Port
Key management as per RFC discussed here:
https://github.com/TF-RMM/tf-rmm/wiki/RFC:-EL3-RMM

feat(rmmd): el3-rmm ide key management interface

Patch introduces the EL3-RMM SMC Interface for Root Port
Key management as per RFC discussed here:
https://github.com/TF-RMM/tf-rmm/wiki/RFC:-EL3-RMM-IDE-KM-Interface

Three IDE Key management smc calls have been added:
- RMM_IDE_KEY_PROG()
- RMM_IDE_KEY_SET_GO()
- RMM_IDE_KEY_SET_STOP()
- RMM_IDE_KM_PULL_RESPONSE()

Due to the absence of root port support in FVP, we are
currently adding placeholders in this patch for the platform
APIs to return success irrespective of the arguments being passed
by the caller(Realms). The SMCs are guarded by
`RMMD_ENABLE_IDE_KEY_PROG` build flag and is disabled by default.
We expect that once the SMCs are stabilized, this build flag will
not be required anymore.

Change-Id: I9411eb7787dac2a207bd14710d251503bd9626ce
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(trng): allow FEAT_RNG_TRAP in dynamic fashion

The documentation promises for ENABLE_FEAT_RNG_TRAP to support the
numeric semantics, with a value of "2" meaning runtime detection. However
two pla

fix(trng): allow FEAT_RNG_TRAP in dynamic fashion

The documentation promises for ENABLE_FEAT_RNG_TRAP to support the
numeric semantics, with a value of "2" meaning runtime detection. However
two places in the build system did not support this, instead were just
checking for a value of "1".

Fix the AArch32 check and build the FVP specific handler routine when
the value is not "0", instead of relying on it to be exactly "1".

Change-Id: I1acd3ed6d2a461d541b9bf57e4aac9c0798ab56b
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "fix(rme): do not trap access to MPAM system registers in Realm mode" into integration

fix(rme): do not trap access to MPAM system registers in Realm mode

Change-Id: I77496ee962727687b28f71a1a15b4fe4133c613c
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>

Merge "build(poetry): install SP dependencies with `--no-root`" into integration

Merge changes from topic "dtpm_poc" into integration

* changes:
feat(docs): update mboot threat model with dTPM
docs(tpm): add design documentation for dTPM
fix(rpi3): expose BL1_RW to BL2 ma

Merge changes from topic "dtpm_poc" into integration

* changes:
feat(docs): update mboot threat model with dTPM
docs(tpm): add design documentation for dTPM
fix(rpi3): expose BL1_RW to BL2 map for mboot
feat(rpi3): add dTPM backed measured boot
feat(tpm): add Infineon SLB9670 GPIO SPI config
feat(tpm): add tpm drivers and framework
feat(io): add generic gpio spi bit-bang driver
feat(rpi3): implement eventlog handoff to BL33
feat(rpi3): implement mboot for rpi3

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