Merge changes from topic "bk/errata_refactor" into integration

* changes:
feat(cpus): wrappers to propagate AArch32 errata info
feat(cpus): add a way to automatically report errata
feat(cpus):

Merge changes from topic "bk/errata_refactor" into integration

* changes:
feat(cpus): wrappers to propagate AArch32 errata info
feat(cpus): add a way to automatically report errata
feat(cpus): add a concise way to implement AArch64 errata
refactor(cpus): convert print_errata_status to C
refactor(cpus): rename errata_report.h to errata.h
refactor(cpus): move cpu_ops field defines to a header

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refactor(cpus): move cpu_ops field defines to a header

The cpu_macros.S file is loaded with lots of definitions for the cpu_ops
structure. However, since they are defined as .equ directives they are

refactor(cpus): move cpu_ops field defines to a header

The cpu_macros.S file is loaded with lots of definitions for the cpu_ops
structure. However, since they are defined as .equ directives they are
inaccessible for C code. Convert them to #defines, put them into order,
refactor them for readability, and extract them to a separate file to
make this possible.

This has the benefit of removing some Aarch differences and a lot of
duplicate code.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I72861794b6c9131285a9297d5918822ed718b228

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Merge "feat(rme): save PAuth context when RME is enabled" into integration

feat(rme): save PAuth context when RME is enabled

This patch enables CTX_INCLUDE_PAUTH_REGS for RME builds.
The RMM-EL3 specification is also updated to reflect the changes
and also version of the s

feat(rme): save PAuth context when RME is enabled

This patch enables CTX_INCLUDE_PAUTH_REGS for RME builds.
The RMM-EL3 specification is also updated to reflect the changes
and also version of the same is bumped from 0.1 to 0.2.

Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: I2e96a592d2b75abaee24294240c1727c5ceba420

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Merge "docs(changelog): changelog for v2.9 release" into integration

docs(changelog): changelog for v2.9 release

Change-Id: Ic8cd82c5424af422feedefdc001d291001817a8b
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

refactor: improve readability of symbol table

Make the symbol table produced by the memory mapping script more
readable. Add a generic interface for interacting with ELF binaries.
This interface ena

refactor: improve readability of symbol table

Make the symbol table produced by the memory mapping script more
readable. Add a generic interface for interacting with ELF binaries.
This interface enables us to get symbols that provide some insights into
TF-A's memory usage.

Change-Id: I6646f817a1d38d6184b837b78039b7465a533c5c
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge changes from topic "mp/feat_ras" into integration

* changes:
refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED
refactor(ras): replace RAS_EXTENSION with FEAT_RAS

Merge changes from topic "srm/Errata_ABI_El3" into integration

* changes:
docs(errata_abi): document the errata abi changes
feat(fvp): enable errata management interface
fix(cpus): workaround

Merge changes from topic "srm/Errata_ABI_El3" into integration

* changes:
docs(errata_abi): document the errata abi changes
feat(fvp): enable errata management interface
fix(cpus): workaround platforms non-arm interconnect
refactor(errata_abi): factor in non-arm interconnect
feat(errata_abi): errata management firmware interface

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Merge changes from topic "bk/context_refactor" into integration

* changes:
fix(gicv3): restore scr_el3 after changing it
refactor(cm): make SVE and SME build dependencies logical

refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED

At the moment we only support FEAT_RAS to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime det

refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED

At the moment we only support FEAT_RAS to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime detection (FEAT_RAS=2), by splitting
is_armv8_2_feat_ras_present() into an ID register reading function and
a second function to report the support status. That function considers
both build time settings and runtime information (if needed), and is
used before we access RAS related registers.

Also move the context saving code from assembly to C, and use the new
is_feat_ras_supported() function to guard its execution.

Change the FVP platform default to the now supported dynamic
option (=2), so the right decision can be made by the code at runtime.

Change-Id: I30498f72fd80b136850856244687400456a03d0e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

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refactor(ras): replace RAS_EXTENSION with FEAT_RAS

The current usage of RAS_EXTENSION in TF-A codebase is to cater for two
things in TF-A :
1. Pull in necessary framework and platform hooks for Firm

refactor(ras): replace RAS_EXTENSION with FEAT_RAS

The current usage of RAS_EXTENSION in TF-A codebase is to cater for two
things in TF-A :
1. Pull in necessary framework and platform hooks for Firmware first
handling(FFH) of RAS errors.
2. Manage the FEAT_RAS extension when switching the worlds.

FFH means that all the EAs from NS are trapped in EL3 first and signaled
to NS world later after the first handling is done in firmware. There is
an alternate way of handling RAS errors viz Kernel First handling(KFH).
Tying FEAT_RAS to RAS_EXTENSION build flag was not correct as the
feature is needed for proper handling KFH in as well.

This patch breaks down the RAS_EXTENSION flag into a flag to denote the
CPU architecture `ENABLE_FEAT_RAS` which is used in context management
during world switch and another flag `RAS_FFH_SUPPORT` to pull in
required framework and platform hooks for FFH.

Proper support for KFH will be added in future patches.

BREAKING CHANGE: The previous RAS_EXTENSION is now deprecated. The
equivalent functionality can be achieved by the following
2 options:
- ENABLE_FEAT_RAS
- RAS_FFH_SUPPORT

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I1abb9ab6622b8f1b15712b12f17612804d48a6ec

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Merge changes from topic "assert_boolean_set" into integration

* changes:
build!: check boolean flags are not empty
fix(build): add a default value for INVERTED_MEMMAP
fix(a5ds): add default v

Merge changes from topic "assert_boolean_set" into integration

* changes:
build!: check boolean flags are not empty
fix(build): add a default value for INVERTED_MEMMAP
fix(a5ds): add default value for ARM_DISABLE_TRUSTED_WDOG
fix(st-crypto): move flag control into source code
fix(stm32mp1): always define PKA algos flags
fix(stm32mp1): remove boolean check on PLAT_TBBR_IMG_DEF

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Merge changes from topics "gr/gcc12", "jc/toolchain_update_2.9" into integration

* changes:
docs(build): update GCC to 12.2.Rel1 version
fix(build): allow lower address access with gcc-12

fix(build): allow lower address access with gcc-12

With gcc-12 any lower address access can trigger a warning/error
this would be useful in other parts of system but in TF-A
there are various reason

fix(build): allow lower address access with gcc-12

With gcc-12 any lower address access can trigger a warning/error
this would be useful in other parts of system but in TF-A
there are various reasons to access to the lower address ranges,
example using mmio_read_*/writes_*

So setup to allow access to lower addresses while using gcc-12

Change-Id: Id1b4012b13bc6876d83b90a347fee12478a1921d
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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refactor(errata_abi): factor in non-arm interconnect

Workaround to help enable the kernel to query errata status using the
errata abi feature for platforms with a non-arm interconnect.

Change-Id: I

refactor(errata_abi): factor in non-arm interconnect

Workaround to help enable the kernel to query errata status using the
errata abi feature for platforms with a non-arm interconnect.

Change-Id: I47b03eaee5a0a763056ae71883fa30dfacb9b3f7
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>

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feat(errata_abi): errata management firmware interface

This patch adds the errata management firmware interface for lower ELs
to discover details about CPU erratum. Based on the CPU erratum
identifi

feat(errata_abi): errata management firmware interface

This patch adds the errata management firmware interface for lower ELs
to discover details about CPU erratum. Based on the CPU erratum
identifier the interface enables the OS to find the mitigation of an
erratum in EL3.

The ABI can only be present in a system that is compliant with SMCCCv1.1
or higher. This implements v1.0 of the errata ABI spec.

For details on all possible return values, refer the design
documentation below:

ABI design documentation:
https://developer.arm.com/documentation/den0100/1-0?lang=en

Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
Change-Id: I70f0e2569cf92e6e02ad82e3e77874546232b89a

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refactor(cm): make SVE and SME build dependencies logical

Currently, enabling SME forces SVE off. However, the SME enablement
requires SVE to be enabled, which is reflected in code. This is the
oppo

refactor(cm): make SVE and SME build dependencies logical

Currently, enabling SME forces SVE off. However, the SME enablement
requires SVE to be enabled, which is reflected in code. This is the
opposite of what the build flags require.

Further, the few platforms that enable SME also explicitly enable SVE.
Their platform.mk runs after the defaults.mk file so this override never
materializes. As a result, the override is only present on the
commandline.

Change it to something sensible where if SME is on then code can rely on
SVE being on too. Do this with a check in the Makefile as it is the more
widely used pattern. This maintains all valid use cases but subtly
changes corner cases no one uses at the moment to require a slightly
different combination of flags.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: If7ca3972ebc3c321e554533d7bc81af49c2472be

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fix(build): add a default value for INVERTED_MEMMAP

It is needed to check the validity of boolean flags with the updated
macro assert_boolean.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Chan

fix(build): add a default value for INVERTED_MEMMAP

It is needed to check the validity of boolean flags with the updated
macro assert_boolean.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I185beb55606a4ca435d2fee2092fc61725859aa1

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Merge "feat(el3-runtime): handle traps for IMPDEF registers accesses" into integration

feat(el3-runtime): handle traps for IMPDEF registers accesses

This patch introduces support to handle traps from lower ELs for
IMPDEF system register accesses. The actual support is left to the
plat

feat(el3-runtime): handle traps for IMPDEF registers accesses

This patch introduces support to handle traps from lower ELs for
IMPDEF system register accesses. The actual support is left to the
platforms to implement.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I623d5c432b4ce4328b68f238c15b1c83df97c1e5

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Merge "feat(sme): enable SME2 functionality for NS world" into integration

chore(rme): add make rule for SPD=spmd

ENABLE_RME is set then SPD must either be spmd or it should not be set.
Add a rule to assert this.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Ch

chore(rme): add make rule for SPD=spmd

ENABLE_RME is set then SPD must either be spmd or it should not be set.
Add a rule to assert this.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I0556e7b0e55b04c3a8e4c20c991fbbc30486570c

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feat(sme): enable SME2 functionality for NS world

FEAT_SME2 is an extension of FEAT_SME and an optional feature
from v9.2. Its an extension of SME, wherein it not only
processes matrix operations ef

feat(sme): enable SME2 functionality for NS world

FEAT_SME2 is an extension of FEAT_SME and an optional feature
from v9.2. Its an extension of SME, wherein it not only
processes matrix operations efficiently, but also provides
outer-product instructions to accelerate matrix operations.
It affords instructions for multi-vector operations.
Further, it adds an 512 bit architectural register ZT0.

This patch implements all the changes introduced with FEAT_SME2
to ensure that the instructions are allowed to access ZT0
register from Non-secure lower exception levels.

Additionally, it adds support to ensure FEAT_SME2 is aligned
with the existing FEATURE DETECTION mechanism, and documented.

Change-Id: Iee0f61943304a9cfc3db8f986047b1321d0a6463
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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Merge "feat(gcs): support guarded control stack" into integration