| #
824e4fa7 |
| 19-Dec-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "chore: drop -fno-builtin" into integration
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| #
ee0c5b8c |
| 09-Dec-2024 |
Boyan Karatotev <boyan.karatotev@arm.com> |
chore: drop -fno-builtin
It is implied by -ffreestanding
Change-Id: Ia7b0f78fd4020aceea246d10ac3d869e743e7a9f Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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| #
62ed5aa0 |
| 13-Dec-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "fix(romlib): romlib build without MbedTLS" into integration
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| #
45db86e0 |
| 12-Dec-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(fpmr): disable FPMR trap" into integration
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| #
a57e18e4 |
| 11-Nov-2024 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
feat(fpmr): disable FPMR trap
This patch enables support of FEAT_FPMR by enabling access to FPMR register. It achieves it by setting the EnFPM bit of SCR_EL3. This feature is currently enabled for N
feat(fpmr): disable FPMR trap
This patch enables support of FEAT_FPMR by enabling access to FPMR register. It achieves it by setting the EnFPM bit of SCR_EL3. This feature is currently enabled for NS world only.
Reference: https://developer.arm.com/documentation/109697/2024_09/ Feature-descriptions/The-Armv9-5-architecture-extension?lang=en
Change-Id: I580c409b9b22f8ead0737502280fb9093a3d5dd2 Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
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| #
8e5a8726 |
| 09-Dec-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "hob_creation_in_tf_a" into integration
* changes: feat(fvp): build hob library feat(lib): introduce Hob creation library feat(lib): modify Hob creation code imported
Merge changes from topic "hob_creation_in_tf_a" into integration
* changes: feat(fvp): build hob library feat(lib): introduce Hob creation library feat(lib): modify Hob creation code imported from edk2 feat(lib): copy StandaloneMm Hob creation library in edk2
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| #
8953568a |
| 13-May-2024 |
Levi Yun <yeoreum.yun@arm.com> |
feat(lib): introduce Hob creation library
According to Platform Initialization (PI) Specification [1] and discussion on edk2 mailing list [2], StandaloneMm shouldn't create Hob but it should be pass
feat(lib): introduce Hob creation library
According to Platform Initialization (PI) Specification [1] and discussion on edk2 mailing list [2], StandaloneMm shouldn't create Hob but it should be passed from TF-A. IOW, TF-A should pass boot information via HOB list to initialise StandaloneMm properly.
And this HOB lists could be delivered via - SPM_MM: Transfer List according to the firmware handoff spec[3]
- FF-A v1.1 >= : FF-A boot protocol.
This patch introduces a TF-A HOB creation library and some of definitions which StandaloneMm requires to boot.
Link: https://uefi.org/sites/default/files/resources/PI_Spec_1_6.pdf [1] Link: https://edk2.groups.io/g/devel/topic/103675962#114283 [2] Link: https://github.com/FirmwareHandoff/firmware_handoff [3] Signed-off-by: Levi Yun <yeoreum.yun@arm.com> Change-Id: I5e0838adce487110206998a8b79bc3adca922cec
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| #
e4a070e3 |
| 03-Dec-2024 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
fix(romlib): romlib build without MbedTLS
The ROMLIB build currently has a strong dependency on MbedTLS. This patch has been introduced to remove this dependency, making it more flexible.
Change-Id
fix(romlib): romlib build without MbedTLS
The ROMLIB build currently has a strong dependency on MbedTLS. This patch has been introduced to remove this dependency, making it more flexible.
Change-Id: If8c4cc7cf557687f40b235a4b8f931cfb70943fd Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| #
f340f3d8 |
| 27-Nov-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes Ibe44f19e,I9e023edb,I96d655fc into integration
* changes: build: use parameters in calls to `MAKE_DEP` build: disable suffix rules globally build: use full paths for generated li
Merge changes Ibe44f19e,I9e023edb,I96d655fc into integration
* changes: build: use parameters in calls to `MAKE_DEP` build: disable suffix rules globally build: use full paths for generated libraries
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| #
daab00cf |
| 03-Sep-2024 |
Chris Kay <chris.kay@arm.com> |
build: disable suffix rules globally
This change centralises the logic that disables the default suffix rules that Make provides. These rules are a hold-over from legacy standards of Make, and occas
build: disable suffix rules globally
This change centralises the logic that disables the default suffix rules that Make provides. These rules are a hold-over from legacy standards of Make, and occasionally conflict with our rules.
Change-Id: I9e023edbc01b5ae48a96fa1078d0b81faabb0cb9 Signed-off-by: Chris Kay <chris.kay@arm.com>
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| #
6e622818 |
| 03-Sep-2024 |
Chris Kay <chris.kay@arm.com> |
build: use full paths for generated libraries
This change modifies the build rules for static libraries so that individual rules which use those libraries depend directly on the archive files that a
build: use full paths for generated libraries
This change modifies the build rules for static libraries so that individual rules which use those libraries depend directly on the archive files that are generated, rather than their phony target aliases and `-lX` link flags.
The goal of this is to clean up Make's view of the dependencies between files, avoiding phony targets (which do not honour timestamps) making their way into intermediate dependencies.
Change-Id: I96d655fcd94dc259ffa6e8970b2be7b8c7e11123 Signed-off-by: Chris Kay <chris.kay@arm.com>
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| #
4ec2948f |
| 20-Nov-2024 |
Govindraj Raja <govindraj.raja@arm.com> |
Merge "docs(changelog): changelog for v2.12 release" into integration
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07a6a654 |
| 15-Nov-2024 |
Govindraj Raja <govindraj.raja@arm.com> |
docs(changelog): changelog for v2.12 release
Generated this change-log using below command: npm run release -- --skip.commit --skip.tag --release-as 2.12.0
Change-Id: Idb74f6a31bf2691e7666e2738030d
docs(changelog): changelog for v2.12 release
Generated this change-log using below command: npm run release -- --skip.commit --skip.tag --release-as 2.12.0
Change-Id: Idb74f6a31bf2691e7666e2738030d6f0e2b8c519 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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7ea8852e |
| 08-Nov-2024 |
Yann Gautier <yann.gautier@st.com> |
Merge changes If56ed0ab,I632236a1 into integration
* changes: perf(build): don't check the compiler's flags for every target perf(build): be clever about uppercasing
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316f5c97 |
| 10-Oct-2024 |
Boyan Karatotev <boyan.karatotev@arm.com> |
perf(build): don't check the compiler's flags for every target
The TF_FLAGS variable must be recursively expanded as the rules that use it are defined before it has been fully defined. That has the
perf(build): don't check the compiler's flags for every target
The TF_FLAGS variable must be recursively expanded as the rules that use it are defined before it has been fully defined. That has the unfortunate side effect of spawning a subshell that calls the compiler for every file that is being built, thrashing multicore build times.
We don't cater to the possibility of the toolchain changing mid build so precomputing this value would be more sensible. Doing a clean build on an Intel dual socket Xeon Gold 5218 (i.e. 64 threads) workstation used to take about 9 seconds. After this patch it takes about 1.5. Single core performance went from ~45 seconds to about 25.
Change-Id: If56ed0ab3cc42bc482d9dd05a41ffbff4dd7f147 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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b40bc36c |
| 07-Nov-2024 |
Yann Gautier <yann.gautier@st.com> |
Merge "build(bl31): support separated memory for RW DATA" into integration
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212993ae |
| 06-Nov-2024 |
Govindraj Raja <govindraj.raja@arm.com> |
Merge "feat(cpufeat): add ENABLE_FEAT_LS64_ACCDATA" into integration
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| #
19d52a83 |
| 09-Aug-2024 |
Andre Przywara <andre.przywara@arm.com> |
feat(cpufeat): add ENABLE_FEAT_LS64_ACCDATA
Armv8.6 introduced the FEAT_LS64 extension, which provides a 64 *byte* store instruction. A related instruction is ST64BV0, which will replace the lowest
feat(cpufeat): add ENABLE_FEAT_LS64_ACCDATA
Armv8.6 introduced the FEAT_LS64 extension, which provides a 64 *byte* store instruction. A related instruction is ST64BV0, which will replace the lowest 32 bits of the data with a value taken from the ACCDATA_EL1 system register (so that EL0 cannot alter them). Using that ST64BV0 instruction and accessing the ACCDATA_EL1 system register is guarded by two SCR_EL3 bits, which we should set to avoid a trap into EL3, when lower ELs use one of those.
Add the required bits and pieces to make this feature usable: - Add the ENABLE_FEAT_LS64_ACCDATA build option (defaulting to 0). - Add the CPUID and SCR_EL3 bit definitions associated with FEAT_LS64. - Add a feature check to check for the existing four variants of the LS64 feature and detect future extensions. - Add code to save and restore the ACCDATA_EL1 register on secure/non-secure context switches. - Enable the feature with runtime detection for FVP and Arm FPGA.
Please note that the *basic* FEAT_LS64 feature does not feature any trap bits, it's only the addition of the ACCDATA_EL1 system register that adds these traps and the SCR_EL3 bits.
Change-Id: Ie3e2ca2d9c4fbbd45c0cc6089accbb825579138a Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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86acbbe2 |
| 26-Aug-2022 |
Ye Li <ye.li@nxp.com> |
build(bl31): support separated memory for RW DATA
Update linker file and init codes to allow using separated memory region for RW DATA. Init codes will copy the RW DATA from the image to the linked
build(bl31): support separated memory for RW DATA
Update linker file and init codes to allow using separated memory region for RW DATA. Init codes will copy the RW DATA from the image to the linked address.
On some NXP platforms, after the BL31 image has been verified, the bl31 image space will be locked/protected as RO only, so need to move the RW DATA and NOBITS out of the bl31 image.
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I361d9a715890961bf30790a3325f8085a40c0c39
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89363219 |
| 28-Oct-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(d128): add support for FEAT_D128" into integration
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| #
30655136 |
| 06-Sep-2024 |
Govindraj Raja <govindraj.raja@arm.com> |
feat(d128): add support for FEAT_D128
This patch disables trapping to EL3 when the FEAT_D128 specific registers are accessed by setting the SCR_EL3.D128En bit.
If FEAT_D128 is implemented, then FEA
feat(d128): add support for FEAT_D128
This patch disables trapping to EL3 when the FEAT_D128 specific registers are accessed by setting the SCR_EL3.D128En bit.
If FEAT_D128 is implemented, then FEAT_SYSREG128 is implemented. With FEAT_SYSREG128 certain system registers are treated as 128-bit, so we should be context saving and restoring 128-bits instead of 64-bit when FEAT_D128 is enabled.
FEAT_SYSREG128 adds support for MRRS and MSRR instruction which helps us to read write to 128-bit system register. Refer to Arm Architecture Manual for further details.
Change the FVP platform to default to handling this as a dynamic option so the right decision can be made by the code at runtime.
Change-Id: I1a53db5eac29e56c8fbdcd4961ede3abfcb2411a Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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5ec9ade9 |
| 21-Oct-2024 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "fix(brbe): allow RME builds with BRBE" into integration
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9890eab5 |
| 18-Oct-2024 |
Boyan Karatotev <boyan.karatotev@arm.com> |
fix(brbe): allow RME builds with BRBE
It used to be the case that a FEAT_RME build could not be built with FEAT_BRBE support. BRBE doesn't have a 3-world aware disable and MDCR_EL3 was not context s
fix(brbe): allow RME builds with BRBE
It used to be the case that a FEAT_RME build could not be built with FEAT_BRBE support. BRBE doesn't have a 3-world aware disable and MDCR_EL3 was not context switched to allow for disabling in Realm world.
As of commit 123002f9171384d976d95935b7f566740d69cc68 MDCR_EL3 is context switched. Since the flag for BRBE support is ENABLE_BRBE_FOR_NS, move brbe_enable() to only happen for NS world. The other worlds will see BRBE disabled and branch recording prohibited. This allows for a build with both RME and BRBE.
Note that EL2 BRBE registers are not context switched. Further work is needed if non-NS support is required.
Change-Id: I82f0f08399dcd080902477dc9636bc4541685f89 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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b6f2e376 |
| 16-Oct-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(sctlr2): add support for FEAT_SCTLR2" into integration
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1cafc96f |
| 16-Oct-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(the): add support for FEAT_THE" into integration
|