core: FS: htree: add rpc final callbacks

Adds rpc final callbacks to struct tee_fs_htree_storage to make the it
possible to isolate the hash tree implementation for test.

Reviewed-by: Etienne Carri

core: FS: htree: add rpc final callbacks

Adds rpc final callbacks to struct tee_fs_htree_storage to make the it
possible to isolate the hash tree implementation for test.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix typo in pager mapping setup

This change fixes a typo in the core mapping setup when pager is enabled.
Looking back in OP-TEE history shows this typo has been there since quite
a while howe

core: fix typo in pager mapping setup

This change fixes a typo in the core mapping setup when pager is enabled.
Looking back in OP-TEE history shows this typo has been there since quite
a while however various build tests based on old code showed the previous
buggy implementation luckily gave valid settings. Yet, it looks far
better once fixed.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: move plat-stm consoles to generic console framework

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

core: move stih UART driver to the drivers/ directory

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

core: arm: imx use early bss attribute for static variable

Use __early_bss attribute for the static variable.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jerome Forissier <jerome.foriss

core: arm: imx use early bss attribute for static variable

Use __early_bss attribute for the static variable.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: fix console drivers against pager

Console operations structures must be kept in the unpaged sections
when pager is enable.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Review

core: fix console drivers against pager

Console operations structures must be kept in the unpaged sections
when pager is enable.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (qemu_virt)

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plat-vexpress: move QEMU SDP test memory to end of the secure RAM

This change restores qemu_armv8 OP-TEE base address to 1Mbyte after
secure RAM base address and moves the qemu_virt and qemu_armv8 S

plat-vexpress: move QEMU SDP test memory to end of the secure RAM

This change restores qemu_armv8 OP-TEE base address to 1Mbyte after
secure RAM base address and moves the qemu_virt and qemu_armv8 SDP
test memory pool to the end of the secure RAM. SDP memory pool
size is increased to 4MByte. TA RAM size is decreased according
to these changes.

Qemu_armv8 reserves the first 1Mbyte of secure RAM to the ARM-TF.
This change fixes the regression introduced by commit df05d4ea7d58
("plat-vexpress: define SDP memory") that assigned back this 1Mbyte
to OP-TEE or SDP memory.

Fixes: df05d4ea7d58 ("plat-vexpress: define SDP memory")
Reported-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (qemu_virt/_armv8)

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Update the maintainer of some i.MX6 and Zynq 7000 boards

Update the maintainer of i.MX6 Quad SABRE Lite, i.MX6 Quad SABRE SD
and Zynq 7000 ZC702.

Signed-off-by: Feng Yu <Yu.Feng@windriver.com>
Revi

Update the maintainer of some i.MX6 and Zynq 7000 boards

Update the maintainer of i.MX6 Quad SABRE Lite, i.MX6 Quad SABRE SD
and Zynq 7000 ZC702.

Signed-off-by: Feng Yu <Yu.Feng@windriver.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
[jf: rebase, reword/reformat commit message, add tags]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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tee_internal_api.h: do not define non-standard macros

The macros SLogTrace(), SLogError(), SLogWarning() and S_VAR_NOT_USED()
are nowhere mentioned in the GlobalPlatform TEE Internal Core API spec.

tee_internal_api.h: do not define non-standard macros

The macros SLogTrace(), SLogError(), SLogWarning() and S_VAR_NOT_USED()
are nowhere mentioned in the GlobalPlatform TEE Internal Core API spec.
Delete them.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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mk/aosp_optee.mk: Allow extra flags for aosp builds

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
[jf: rebase on top of master]
Signed

mk/aosp_optee.mk: Allow extra flags for aosp builds

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
[jf: rebase on top of master]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: arm: imx: correct PCR settings

According to Cortex A9 TRM, bit[10:8] of PCR is max_clk_latency:
Samples the value present on the MAXCLKLATENCY pins on exit from reset.
This value reflects an i

core: arm: imx: correct PCR settings

According to Cortex A9 TRM, bit[10:8] of PCR is max_clk_latency:
Samples the value present on the MAXCLKLATENCY pins on exit from reset.
This value reflects an implementation-specific parameter.
ARM strongly recommends that the software does not modify it.

So change the value to 0 is not wise, correct it.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: add support for i.MX6 Dual Lite SabreSD

Signed-off-by: Mathieu Briand <mbriand@witekio.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.car

core: arm: add support for i.MX6 Dual Lite SabreSD

Signed-off-by: Mathieu Briand <mbriand@witekio.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

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core: arm: trace: make the trace output atomic

Use spinlock to make the trace output atomic.
On SMP cores, different cores may puts out log
to uart. If there is no lock, the log will be a mess.

Whe

core: arm: trace: make the trace output atomic

Use spinlock to make the trace output atomic.
On SMP cores, different cores may puts out log
to uart. If there is no lock, the log will be a mess.

When there is a contention, print out a '*'.

Need to disable interrupt, because cpu_spin_lock/unlock/trylock
will invoke assert with CFG_TEE_CORE_DEBUG=y. So
mask interrupt before lock, then un-mask interrupt after unlock.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (HiKey)
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: arm64: support relocation type R_AARCH64_ABS64 (257)

If a 64-bit TA contains relocations of type R_AARCH64_ABS64, OP-TEE
refuses to load it and logs the following error:

ERROR: TEE-CORE:

core: arm64: support relocation type R_AARCH64_ABS64 (257)

If a 64-bit TA contains relocations of type R_AARCH64_ABS64, OP-TEE
refuses to load it and logs the following error:

ERROR: TEE-CORE: Unknown relocation type 257

This relocation type does not seem to happen in our test applications,
but someone has experienced the issue after linking a TA against a
third-party static library [1]. I could reproduce the issue by
compiling the hello_world TA with -fPIC instead of -fpie. This simple
change generates *one* R_AARCH64_ABS64 in the TA ELF file.

This commit adds the necessary code to support R_AARCH64_ABS64.

[1] https://github.com/OP-TEE/optee_os/issues/1399

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (qemu_v8)
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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doc: fix link and few spellings

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

core: export pTA invoke_tests API to ease tests integration

Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome

core: export pTA invoke_tests API to ease tests integration

Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pTA SDP memref parameters are reserved to secure clients

Accessing SDP memory from a pseudo TA is a secure service reserved
to the secure clients. pseudo TAs involved in Secure Data Path setup

core: pTA SDP memref parameters are reserved to secure clients

Accessing SDP memory from a pseudo TA is a secure service reserved
to the secure clients. pseudo TAs involved in Secure Data Path setups
are expected to provide services for secure clients only: SDP TAs.

SDP memory are default not mapped in the core virtual mapping. When
a pTA is invoked from a TA, the pTA uses the TA virtual mapping to
access memref parameter buffers. When a pTA is invoked from the non
secure world, the sequence relies on core virtual mapping. such SDP
references would needed to be mapped. This is NOT supported in
current implementation. Mapping SDP memref in the core will be
implemented only once contributors really claim for such a support.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add cache maintenance to invocation test pseudo TA

Invocation test pseudo TA can be used to test SDP memory accesses
from pseudo TAs. As SDP memory access may need cache maintenance,
such main

core: add cache maintenance to invocation test pseudo TA

Invocation test pseudo TA can be used to test SDP memory accesses
from pseudo TAs. As SDP memory access may need cache maintenance,
such maintenance support is added to this test pseudo TA.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: rename pseudo TA used for invocation tests

Pseudo TA "selftest" is mainly used to test invocation of pseudo
TAs. Hence rename it 'invocation tests' pseudo TA.

Signed-off-by: Etienne Carriere

core: rename pseudo TA used for invocation tests

Pseudo TA "selftest" is mainly used to test invocation of pseudo
TAs. Hence rename it 'invocation tests' pseudo TA.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: invocation test pseudo TA participates in SDP tests

Add inject/transform/dump commands support to the invocation test
pseudo TA based on the "SDP basic test" setup from xtest. This change
allo

core: invocation test pseudo TA participates in SDP tests

Add inject/transform/dump commands support to the invocation test
pseudo TA based on the "SDP basic test" setup from xtest. This change
allows to test invocation of a pseudo TA with SDP memory references
from a user TA.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: allow pseudo TA to access SDP memory references

This change also enables the SDP property for the pseudo TA used
to test invocation of pseudo TAs in non-regression tests infrastructure.

Signe

core: allow pseudo TA to access SDP memory references

This change also enables the SDP property for the pseudo TA used
to test invocation of pseudo TAs in non-regression tests infrastructure.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: syscall_storage_reset_enum() must check e->fops before using it

An object enumerator that has just been allocated or reset has its fops
field set to NULL. So, syscall_storage_reset_enum() must

core: syscall_storage_reset_enum() must check e->fops before using it

An object enumerator that has just been allocated or reset has its fops
field set to NULL. So, syscall_storage_reset_enum() must take care of
this.

Fixes: https://github.com/OP-TEE/optee_os/issues/1417
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: rename mem_param into param_mem for consistency

Reported-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Fo

core: rename mem_param into param_mem for consistency

Reported-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-stm: add a default test support for SDP

If SDP is enabled and no SDP memory is defined, a default SDP memory
area of 3Mbyte is defined between the TA_RAM and the NS_SHM. This
change allows to e

plat-stm: add a default test support for SDP

If SDP is enabled and no SDP memory is defined, a default SDP memory
area of 3Mbyte is defined between the TA_RAM and the NS_SHM. This
change allows to ease test of the SDP feature on the ST platforms.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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travis: add build test with CFG_SECURE_DATA_PATH=y

Add testing build for vexpress-qemu_virt platform with the secure
data path feature enabled.

Signed-off-by: Etienne Carriere <etienne.carriere@lin

travis: add build test with CFG_SECURE_DATA_PATH=y

Add testing build for vexpress-qemu_virt platform with the secure
data path feature enabled.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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