core: plat-vexpress: increase CFG_TEE_RAM_VA_SIZE

Increases CFG_TEE_RAM_VA_SIZE to 2 MiB for the plat-vexpress platforms.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens

core: plat-vexpress: increase CFG_TEE_RAM_VA_SIZE

Increases CFG_TEE_RAM_VA_SIZE to 2 MiB for the plat-vexpress platforms.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU v7)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: deal with large CFG_TEE_RAM_VA_SIZE

Deals with CFG_TEE_RAM_VA_SIZE > CORE_MMU_PGDIR_SIZE. This is a special
problem as the pages managed by the pager then spans several translation
tabl

core: pager: deal with large CFG_TEE_RAM_VA_SIZE

Deals with CFG_TEE_RAM_VA_SIZE > CORE_MMU_PGDIR_SIZE. This is a special
problem as the pages managed by the pager then spans several translation
tables.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: free pages across multiple areas

Changes tee_pager_release_phys() to handle freeing a range of pages spanning
multiple areas.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org

core: pager: free pages across multiple areas

Changes tee_pager_release_phys() to handle freeing a range of pages spanning
multiple areas.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: move some internal functions

Moves some internal functions inside the pager code to prepare for a
future commit.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-

core: pager: move some internal functions

Moves some internal functions inside the pager code to prepare for a
future commit.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add MEM_AREA_PAGER_VASPACE

Adds MEM_AREA_PAGER_VASPACE which is used to create empty translation
tables as needed for the pager.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Si

core: add MEM_AREA_PAGER_VASPACE

Adds MEM_AREA_PAGER_VASPACE which is used to create empty translation
tables as needed for the pager.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: update tee_pager_add_core_area()

All failures in tee_pager_add_core_area() are fatal. Replaces return
code with void and panics on errors instead.

Reviewed-by: Etienne Carriere <etienn

core: pager: update tee_pager_add_core_area()

All failures in tee_pager_add_core_area() are fatal. Replaces return
code with void and panics on errors instead.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: hide tee_pager_tbl_info

Hides tee_pager_tbl_info and provides new needed functions.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wikl

core: pager: hide tee_pager_tbl_info

Hides tee_pager_tbl_info and provides new needed functions.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add CORE_MMU_PGDIR_LEVEL

Adds the define CORE_MMU_PGDIR_LEVEL which indicates the level used for
page directories.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: J

core: add CORE_MMU_PGDIR_LEVEL

Adds the define CORE_MMU_PGDIR_LEVEL which indicates the level used for
page directories.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: make tee_mm_vcore cover TEE_RAM only

Prior to this patch was tee_mm_vcore initialized to cover the complete
page directories covering TEE_RAM. With this patch tee_mm_vcore will
only cover TEE_

core: make tee_mm_vcore cover TEE_RAM only

Prior to this patch was tee_mm_vcore initialized to cover the complete
page directories covering TEE_RAM. With this patch tee_mm_vcore will
only cover TEE_RAM in order to avoid returning unexpected addresses when
allocating.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vextpress: fvp: map tzcdram

Map part of DRAM as TZCDRAM in sync with ARM-TF. This is needed to be
able to read pageable part supplied by ARM-TF when pager is enabled.

Reviewed-by: Joakim Bech

plat-vextpress: fvp: map tzcdram

Map part of DRAM as TZCDRAM in sync with ARM-TF. This is needed to be
able to read pageable part supplied by ARM-TF when pager is enabled.

Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Add support for compressed early TAs

Add decompression code to the early TA loader and update the Python
script accordingly. The compression algorithm is "deflate", which is
used by zlib and gzip in

Add support for compressed early TAs

Add decompression code to the early TA loader and update the Python
script accordingly. The compression algorithm is "deflate", which is
used by zlib and gzip in particular. It allows for compression ratios
comprised between 3 (for bigger TAs) and 4.7 (for smaller ones). Those
numbers were observed with 32-bit TAs (QEMU).

On QEMU (armv7), the code size overhead when CFG_EARLY_TA=y, including
the decompressor, is 12K when DEBUG=0 or 20K when DEBUG=1. The
decompressor allocates about 39K of heap.

Another library compatible with zlib was tried for comparison [1].
The code size overhead with miniz was 8K (DEBUG=0) or 16K (DEBUG=1).
On the other hand, the dynamic allocation was about 43K, so the total
memory required was about same. Speed was not compared. In the end,
zlib was preferred for licensing reasons and because it is widely used.

Link: [1] https://github.com/richgel999/miniz
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (QEMU)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (QEMUv8, pager)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (D02 32/64 bits)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (D02 32/64 bits, pager)
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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Import zlib v1.2.11

Import the decompression code from zlib v1.2.11. From the project's
README:

"zlib 1.2.11 is a general purpose data compression library. [...] The
data format used by the zlib li

Import zlib v1.2.11

Import the decompression code from zlib v1.2.11. From the project's
README:

"zlib 1.2.11 is a general purpose data compression library. [...] The
data format used by the zlib library is described by RFCs (Request for
Comments) 1950 to 1952 in the files rfc1950 (zlib format), rfc1951
(deflate format) and rfc1952 (gzip format)."

This code will be used in a later commit to decompress early TAs.
Only the inflate() function is needed, and the library is configured
without gzip support. The source files that are not required
for inflate() are left aside.

The library is licensed under a permissive license, see `zlib.h`.

Link: http://tools.ietf.org/html/rfc1950
Link: http://tools.ietf.org/html/rfc1951
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: link.mk: force link of tee.elf when object list has changed

Since the parent commit ("Add support for early Trusted Applications"),
the link step of tee.elf may pull object files generated fro

core: link.mk: force link of tee.elf when object list has changed

Since the parent commit ("Add support for early Trusted Applications"),
the link step of tee.elf may pull object files generated from Trusted
Application binaries. This is controlled by $(EARLY_TA_PATHS). Adding
or removing files should cause tee.elf to be re-linked, even when no
re-compilation or change in the configuration variables occur. This is
not the case currently. For example:
$ make EARLY_TA_PATHS="a.elf b.elf"
$ make EARLY_TA_PATHS="a.elf" # Should re-link without b.elf

The link recipe is modified so that the link step is forced when the
object list changes.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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Add support for early Trusted Applications

Early TAs are user-mode Trusted Applications that are embedded at link
time in the TEE binary. A special read-only data section is used to
store them (.rod

Add support for early Trusted Applications

Early TAs are user-mode Trusted Applications that are embedded at link
time in the TEE binary. A special read-only data section is used to
store them (.rodata.early_ta). A Python script takes care of converting
the TAs into a C source file with the proper linker section attribute.

The feature is disabled by default. To enable it, the paths to the TA
binaries have to be given in $(EARLY_TA_PATHS). They should be ELF
files. Typical build steps:
$ make ... CFG_EARLY_TA=y ta_dev_kit # (1)
$ # ... build the TAs ... # (2)
$ make ... EARLY_TA_PATHS=path/to/<uuid>.stripped.elf # (3)
Notes:
- Setting CFG_EARLY_TA=y during the first step (1) is not necessary,
but it will avoid rebuilding libraries during the third step (3)
- CFG_EARLY_TA is automatically enabled when EARLY_TA_PATHS is non-empty
in step (3)
- Several TAs may be given in $(EARLY_TA_PATHS) (3)

Early TAs are given a higher load priority than REE FS TAs, since they
should be available even before tee-supplicant is ready.

Suggested-by: Zeng Tao <prime.zeng@hisilicon.com>
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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Add support for several user TA stores

Replace the pointer to the user-mode TA load operations with a list
so that several implementations may be used simultaneously. Each store
has its own priority

Add support for several user TA stores

Replace the pointer to the user-mode TA load operations with a list
so that several implementations may be used simultaneously. Each store
has its own priority.
Make tee_ta_init_user_ta_session() iterate on the list and stop as
soon as a matching TA is found.
This is preparatory work for the introduction of a new TA store.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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Add description string to user_ta_store_ops

In preparation for the introduction of a new TA store type, add a
description string to the user_ta_store_ops structure and print it when
a user-mode TA i

Add description string to user_ta_store_ops

In preparation for the introduction of a new TA store type, add a
description string to the user_ta_store_ops structure and print it when
a user-mode TA is being loaded.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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Add target ta_dev_kit

Adds support for `make ta_dev_kit`, to build the user space libraries
only and copy them (as well as the related header files and make files)
to the export directory.

Signed-o

Add target ta_dev_kit

Adds support for `make ta_dev_kit`, to build the user space libraries
only and copy them (as well as the related header files and make files)
to the export directory.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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Remove leading spaces and dots in DMSG() messages

Some debug messages have various amounts of leading spaces and dots
(.) probably in an attempt to better align the text. It is unreliable
because de

Remove leading spaces and dots in DMSG() messages

Some debug messages have various amounts of leading spaces and dots
(.) probably in an attempt to better align the text. It is unreliable
because debug traces include function names and line numbers, which
introduce random offsets. Remove these characters.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core/sub.mk: add missing dependency on the TA key processing script

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by:

core/sub.mk: add missing dependency on the TA key processing script

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: fix unwind in PSCI

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

core: clean and unwind arm32_aeabi_[l]divmod_a32.S

Division support can be used in kernel land and user land. Kernel
land already support unwind on assembly (kernel/unwind.h) but
userland do not. Fo

core: clean and unwind arm32_aeabi_[l]divmod_a32.S

Division support can be used in kernel land and user land. Kernel
land already support unwind on assembly (kernel/unwind.h) but
userland do not. For simplicity of the userland part, simply
define local macros to support unwind in both conditions.

Clean ldivmod from locally defined macros already provided by arm.S.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add matches operation to mobj_paged_ops

Adds the matches operation to mobj_paged_ops in order to correctly
classify paged MOBJs.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Te

core: add matches operation to mobj_paged_ops

Adds the matches operation to mobj_paged_ops in order to correctly
classify paged MOBJs.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add matches operation to mobj_reg_shm_ops

Adds the matches operation to mobj_reg_shm_ops in order to correctly
classify reg_shm MOBJs.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.o

core: add matches operation to mobj_reg_shm_ops

Adds the matches operation to mobj_reg_shm_ops in order to correctly
classify reg_shm MOBJs.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix memory address comparison

Addresses are unsigned values. Subtracting address values results
in an unsigned value. Since qsort comparison function expects a signed
integer return value, the

core: fix memory address comparison

Addresses are unsigned values. Subtracting address values results
in an unsigned value. Since qsort comparison function expects a signed
integer return value, the unsigned address subtraction value gets
signed and can produce a wrong result. This change overcomes the issue
by producing a +1/0/-1 signed value based on the address unsigned
values comparison.

Introduce CMP_TRILEAN() in util.h to implement the operation.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260)
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: default enable program flow prediction on ARMv7 cores

Introduce CFG_ENABLE_SCTLR_Z to enable SCTLR[Z] from the generic boot.
SCTLR[Z] enables program flow prediction support from the core.

Ea

core: default enable program flow prediction on ARMv7 cores

Introduce CFG_ENABLE_SCTLR_Z to enable SCTLR[Z] from the generic boot.
SCTLR[Z] enables program flow prediction support from the core.

Early branch prediction may be unsafe against uncontrolled memory
prefetches that could hit some hard memory access control firewalls.
It is usually safer to enable after the mmu is enabled.

CFG_ENABLE_SCTLR_Z allows to use vanilla op-tee on development board
to exercises benchmark and performance tests over the op-tee system.

This feature is no expected on ARMv8 architectures and some recent
ARMv7 architectures since program flow prediction enable is tight to
mmu enable.

Suggested-by: Jangseop Shin <jsshin@sor.snu.ac.kr>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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