doc: review interrupts_handling

interrupts_handling.md covers interrupts (IRQ/FIQ) and SMC exceptions.
Clean title and state it from the introduction the document coverage.

Review sections split to

doc: review interrupts_handling

interrupts_handling.md covers interrupts (IRQ/FIQ) and SMC exceptions.
Clean title and state it from the introduction the document coverage.

Review sections split to clarify content.
Detail main routing of IRQ, FIQ and SMC events.
Clarify Monitor in ARMv7/ARMv8 cases.

Use 'trusted thread' to refer the threads management in OP-TEE core.

Add a section about OP-TEE thread scheduling.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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qemu_virt: enable smp boot

Enables SMP boot of the plat-vexpress qemu_virt flavor. This includes
PSCI support and coherent memory shared with bios.

Acked-by: Jerome Forissier <jerome.forissier@lina

qemu_virt: enable smp boot

Enables SMP boot of the plat-vexpress qemu_virt flavor. This includes
PSCI support and coherent memory shared with bios.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: generic boot: update fdt with psci

If configured with device tree and PSCI update the FDT with PSCI nodes
and other information needed by the kernel to start up the secondary
cores.

Acked-by:

core: generic boot: update fdt with psci

If configured with device tree and PSCI update the FDT with PSCI nodes
and other information needed by the kernel to start up the secondary
cores.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: plat-vextpress-qemu_virt: update num cores

Changes number of supported cores for variant qemu_virt to 4.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander

core: plat-vextpress-qemu_virt: update num cores

Changes number of supported cores for variant qemu_virt to 4.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: plat-vexpress: init gic on secondary cores

Initialize GIC on secondary cores if not configured with ARM-TF.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklan

core: plat-vexpress: init gic on secondary cores

Initialize GIC on secondary cores if not configured with ARM-TF.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: make reset_secondary() unpaged

reset_secondary() and dependencies has to be unpaged as most of it is
executed before the core has been properly configured to use the pager.

Acked-by: Jerome F

core: make reset_secondary() unpaged

reset_secondary() and dependencies has to be unpaged as most of it is
executed before the core has been properly configured to use the pager.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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scripts/symbolize.py: print ELF sections after MMU region information

When processing a user TA abort dump, list the ELF sections that are
mapped in each MMU region. For example (the lines modified

scripts/symbolize.py: print ELF sections after MMU region information

When processing a user TA abort dump, list the ELF sections that are
mapped in each MMU region. For example (the lines modified by this
patch are prefixed with >>):

User TA undef-abort at address 0x10574e
fsr 0x00000000 ttbr0 0x0e07a06a ttbr1 0x0e07406a cidr 0x1
cpu #0 cpsr 0x60000030
r0 0x20000013 r4 0x0013a6bc r8 0x00000000 r12 0x0e07dd88
r1 0x00000033 r5 0x00121fd3 r9 0x00000000 sp 0x001026cc
r2 0x0010581f r6 0x00102590 r10 0x00000000 lr 0x00105823
r3 0x00000043 r7 0x001026cc r11 0x00000000 pc 0x0010574e
Status of TA 5b9e0e40-2636-11e1-ad9e-0002a5d5c51b (0xe073b70) (active)
arch: arm load address: 0x103000 ctx-idr: 1
stack: 0x100000 10240
region 0: va 0x100000 pa 0xe21e000 size 0x3000 flags rw-
>> region 1: va 0x103000 pa 0xe100000 size 0x2e000 flags r-x .ta_head .text .rodata
>> region 2: va 0x131000 pa 0xe12e000 size 0xa000 flags r-- .rodata .ARM.extab .ARM.exidx .got .dynsym .rel.got .dynamic .dynstr .hash .rel.dyn
>> region 3: va 0x13b000 pa 0xe138000 size 0xe6000 flags rw- .data .bss
region 4: va 0 pa 0 size 0 flags ---
region 5: va 0 pa 0 size 0 flags ---
region 6: va 0 pa 0 size 0 flags ---
region 7: va 0 pa 0 size 0 flags ---
User TA undef-abort at address 0x10574e undef_instr+6 .text+10030
Call stack:
0x0010574e undef_instr at optee_test/ta/os_test/os_test.c:880
0x00105823 ta_entry_bad_mem_access at optee_test/ta/os_test/os_test.c:917
0x00105e75 TA_InvokeCommandEntryPoint at optee_test/ta/os_test/ta_entry.c:101
0x00121fb7 entry_invoke_command at optee_os/lib/libutee/arch/arm/user_ta_entry.c:207
0x00122013 __utee_entry at optee_os/lib/libutee/arch/arm/user_ta_entry.c:235

Suggested-by: Zeng Tao <prime.zeng@hisilicon.com>
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: print rwx flags for each MMU region when a user TA aborts

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

core: arm: imx7d: add psci suspend support

Implement i.MX7D suspend/resume support.
When the first time runs into suspend, some initialization work needs
to be done, such as code copy, iram translat

core: arm: imx7d: add psci suspend support

Implement i.MX7D suspend/resume support.
When the first time runs into suspend, some initialization work needs
to be done, such as code copy, iram translation table.

Since we only have 32K on chip RAM for suspend/resume usage, we have
to put code and data together and use section mapping and WXN is set
to false.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: arm: imx7d: remove soc_is_imx7d/s functions

Remove soc_is_imx7d/s functions. Not needed.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-

core: arm: imx7d: remove soc_is_imx7d/s functions

Remove soc_is_imx7d/s functions. Not needed.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: arm: sm: add psci power state macros

Add PSCI_POWER_STATE_X macros

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carr

core: arm: sm: add psci power state macros

Add PSCI_POWER_STATE_X macros

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: arm: imx: get mmdc type

Add get mmdc type support, this will be used when configuring
ddr into self refresh for low power feature.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jens Wi

core: arm: imx: get mmdc type

Add get mmdc type support, this will be used when configuring
ddr into self refresh for low power feature.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: imx: simplify code

Wrap memory registration using macros to make it easy to add new soc/arch
support.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linar

core: imx: simplify code

Wrap memory registration using macros to make it easy to add new soc/arch
support.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: imx7: fix comments

Fix comments.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

core: arm: imx: move psci code to pm

Move psci code to pm.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.car

core: arm: imx: move psci code to pm

Move psci code to pm.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: arm: psci: add suspend resume common functions

Add cpu suspend/resume common functions.

Platform psci suspend functions need to call
sm_pm_cpu_suspend(arg, platform_suspend) to runs into susp

core: arm: psci: add suspend resume common functions

Add cpu suspend/resume common functions.

Platform psci suspend functions need to call
sm_pm_cpu_suspend(arg, platform_suspend) to runs into suspend.

The i.MX flow is:
psci_cpu_suspend->imx7_cpu_suspend->sm_pm_cpu_suspend(arg, func)
The "func" runs in on-chip ram that not losing power when
system runs into suspend or low power state. Argument "arg" is
passed to function "func" as argument through register "r0".

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: arm: kernel: make thread_core_local public

Move the struture of thread_core_local from thread_private.h
to thread.h to make it public.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by:

core: arm: kernel: make thread_core_local public

Move the struture of thread_core_local from thread_private.h
to thread.h to make it public.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: arm: psci: pass nsec ctx to psci

Pass non-secure context to psci functions. When cpu/system suspends,
cpu may loose power, so when back to linux from tee, tee
needs to return to a linux resume

core: arm: psci: pass nsec ctx to psci

Pass non-secure context to psci functions. When cpu/system suspends,
cpu may loose power, so when back to linux from tee, tee
needs to return to a linux resume point, not the usual return address
after "smc" instruction. So we need to modify the mon_lr
value in non-secure context.

Psci runs in monitor mode, sm_get_nsec_ctx can not be used,
so pass the non-secure context pointer to the psci suspend function.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: mmu: export map_memarea_sections

Export map_memarea_sections. We need a mmu table
dedicated for low power feature, so export
map_memarea_sections to create that section mapping.

Signed-off-by

core: mmu: export map_memarea_sections

Export map_memarea_sections. We need a mmu table
dedicated for low power feature, so export
map_memarea_sections to create that section mapping.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: introduce get_core_pos_mpidr()

Adds
size_t get_core_pos_mpidr(uint32_t mpidr);
which translates from mpdir to core position, like get_core_pos() does
for the calling core.

get_core_pos_mpidr(

core: introduce get_core_pos_mpidr()

Adds
size_t get_core_pos_mpidr(uint32_t mpidr);
which translates from mpdir to core position, like get_core_pos() does
for the calling core.

get_core_pos_mpidr() a weak function to
allow platforms to override the implementation.

get_core_pos() now uses get_core_pos_mpidr() internally to calculate the
core position without using any stack.

With get_core_pos_mpidr() all the platform specific implementations of
get_core_pos() has been replaced with get_core_pos_mpidr() and
get_core_pos() is not weak any longer to avoid unexpected runtime errors
in out of tree rebased platforms.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU v8)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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docs: update porting guidelines regarding pager support

ARM64 supports pager.

Prefer including core_mmu.h rather than core_memprot.h to
declare register_phys_mem() support.

Remove useless include

docs: update porting guidelines regarding pager support

ARM64 supports pager.

Prefer including core_mmu.h rather than core_memprot.h to
declare register_phys_mem() support.

Remove useless include of tee_pager.h.

Reported-by: Kevin Peng <kevinp@marvell.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: fix build errors

Fix build errors in plat-imc/imx6.c and plat-imx/psci.c

Fixes: 6a815afa16230 ("core: introduce TEE_RAM_VA_START and TEE_TEXT_VA_START")
Signed-off-by: Jerome Forissier <

core: imx: fix build errors

Fix build errors in plat-imc/imx6.c and plat-imx/psci.c

Fixes: 6a815afa16230 ("core: introduce TEE_RAM_VA_START and TEE_TEXT_VA_START")
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: asan: tag access for .ARM.extab and .ARM.exidx

The two sections .ARM.extab and .ARM.exidx are accessed when printing a
stack trace. Tag access for these two sections to avoid recursive panics

core: asan: tag access for .ARM.extab and .ARM.exidx

The two sections .ARM.extab and .ARM.exidx are accessed when printing a
stack trace. Tag access for these two sections to avoid recursive panics
due to failing checks against shadow area.

Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: asan: fix check_access()

Prior to this patch the for loop in check_access() that checks the
access in the shadow area is skipping accesses smaller than a ASAN block
(8 bytes). This patch fixes

core: asan: fix check_access()

Prior to this patch the for loop in check_access() that checks the
access in the shadow area is skipping accesses smaller than a ASAN block
(8 bytes). This patch fixes that problem and checks also smaller
accesses.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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libutils: malloc: use asan_memset_unchecked()

The malloc implementation uses the new asan_memset_unchecked() function
internally instead of memset() to avoid unexpected asserts when the
address sani

libutils: malloc: use asan_memset_unchecked()

The malloc implementation uses the new asan_memset_unchecked() function
internally instead of memset() to avoid unexpected asserts when the
address sanitizer is enabled.

bget() tags the requested amount of memory allocated, but eventual
padding etc isn't tagged so writes there from instrumented functions,
for instance the normal memset(), will be caught.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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