xref: /optee_os/core/arch/arm/kernel/misc_a32.S (revision 3037280085026f61d52bccff261f8d47614d5d33)
1/*
2 * Copyright (c) 2014, STMicroelectronics International N.V.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#include <asm.S>
29#include <arm.h>
30#include <arm32_macros.S>
31#include <kernel/unwind.h>
32
33/* Let platforms override this if needed */
34.weak get_core_pos_mpidr
35
36/* size_t get_core_pos(void); */
37FUNC get_core_pos , :
38UNWIND(	.fnstart)
39	read_mpidr r0
40	b get_core_pos_mpidr
41UNWIND(	.fnend)
42END_FUNC get_core_pos
43
44/* size_t get_core_pos_mpidr(uint32_t mpidr); */
45FUNC get_core_pos_mpidr , :
46UNWIND(	.fnstart)
47	/* Calculate CorePos = (ClusterId * 4) + CoreId */
48	and	r1, r0, #MPIDR_CPU_MASK
49	and	r0, r0, #MPIDR_CLUSTER_MASK
50	add	r0, r1, r0, LSR #6
51	bx	lr
52UNWIND(	.fnend)
53END_FUNC get_core_pos_mpidr
54
55/*
56 * uint32_t temp_set_mode(int cpu_mode)
57 *   returns cpsr to be set
58 */
59LOCAL_FUNC temp_set_mode , :
60UNWIND(	.fnstart)
61	mov	r1, r0
62	cmp	r1, #CPSR_MODE_USR	/* update mode: usr -> sys */
63	moveq	r1, #CPSR_MODE_SYS
64	cpsid	aif			/* disable interrupts */
65	mrs	r0, cpsr		/* get cpsr with disabled its*/
66	bic	r0, #CPSR_MODE_MASK	/* clear mode */
67	orr	r0, r1			/* set expected mode */
68	bx	lr
69UNWIND(	.fnend)
70END_FUNC temp_set_mode
71
72/* uint32_t read_mode_sp(int cpu_mode) */
73FUNC read_mode_sp , :
74UNWIND(	.fnstart)
75	push	{r4, lr}
76UNWIND(	.save	{r4, lr})
77	mrs	r4, cpsr		/* save cpsr */
78	bl	temp_set_mode
79	msr	cpsr, r0		/* set the new mode */
80	mov	r0, sp			/* get the function result */
81	msr	cpsr, r4		/* back to the old mode */
82	pop	{r4, pc}
83UNWIND(	.fnend)
84END_FUNC read_mode_sp
85
86/* uint32_t read_mode_lr(int cpu_mode) */
87FUNC read_mode_lr , :
88UNWIND(	.fnstart)
89	push	{r4, lr}
90UNWIND(	.save	{r4, lr})
91	mrs	r4, cpsr		/* save cpsr */
92	bl	temp_set_mode
93	msr	cpsr, r0		/* set the new mode */
94	mov	r0, lr			/* get the function result */
95	msr	cpsr, r4		/* back to the old mode */
96	pop	{r4, pc}
97UNWIND(	.fnend)
98END_FUNC read_mode_lr
99